mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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stm32f10x: Initial import
This adds initial support for the other chips in the stm32f10x series: stm32f101, stm32f102x, stm32f103x, stm32f105x, stm32f107x. The main difference is in the register definitions. Clock, flash, GPIO, and JTAG modules are similar enough that for now we can symlink the existing source for stm32f100. BRANCH=none BUG=none TEST=Tested on McCroskey (follow-up CL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I67363d02578e21be51d842b6bd8b5e4848720993 Reviewed-on: https://gerrit.chromium.org/gerrit/43412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks
committed by
ChromeBot
ChromeBot
parent
a44e0d91c8
commit
ea000b0fc0
1
chip/stm32/clock-stm32f10x.c
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1
chip/stm32/clock-stm32f10x.c
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@@ -0,0 +1 @@
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clock-stm32f100.c
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40
chip/stm32/config-stm32f10x.h
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40
chip/stm32/config-stm32f10x.h
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@@ -0,0 +1,40 @@
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/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Memory mapping */
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#define CONFIG_FLASH_BASE 0x08000000
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#define CONFIG_FLASH_PHYSICAL_SIZE 0x00010000
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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#define CONFIG_FLASH_BANK_SIZE 0x1000
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#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE (10 * 1024)
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/* Size of one firmware image in flash */
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#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
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#define CONFIG_FW_RO_OFF 0
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#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
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- CONFIG_SECTION_FLASH_PSTATE_SIZE)
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#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
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#define CONFIG_SECTION_RO_OFF CONFIG_FW_RO_OFF
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#define CONFIG_SECTION_RO_SIZE CONFIG_FW_RO_SIZE
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#define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF
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#define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE
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#define CONFIG_SECTION_WP_RO_OFF CONFIG_FW_RO_OFF
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#define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
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/*
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* Put this after RO to give RW more space. This also makes RO write protect
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* region contiguous.
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*/
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#define CONFIG_SECTION_FLASH_PSTATE_SIZE (1 * CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 68
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@@ -10,7 +10,11 @@
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#if defined(CHIP_VARIANT_stm32l15x)
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#include "config-stm32l15x.h"
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#elif defined(CHIP_VARIANT_stm32f100)
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/* STM32F100xx is currently the only outlier in the STM32F series */
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#include "config-stm32f100.h"
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#elif defined(CHIP_VARIANT_stm32f10x)
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/* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx, and STM32F107xx */
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#include "config-stm32f10x.h"
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#else
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#error "Unsupported chip variant"
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#endif
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1
chip/stm32/flash-stm32f10x.c
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1
chip/stm32/flash-stm32f10x.c
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@@ -0,0 +1 @@
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flash-stm32f100.c
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1
chip/stm32/gpio-stm32f10x.c
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1
chip/stm32/gpio-stm32f10x.c
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@@ -0,0 +1 @@
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gpio-stm32f100.c
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@@ -16,10 +16,8 @@
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/* Divider to get microsecond for the clock */
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#define CLOCKSOURCE_DIVIDER (CPU_CLOCK / SECOND)
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#ifdef CHIP_VARIANT_stm32f100
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#define TIM_WD_IRQ STM32_IRQ_TIM1_UP_TIM16
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#define TIM_WD 1 /* Timer to use for watchdog */
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#endif
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/*
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* TIM_CLOCK_MSB and TIM_CLOCK_LSB must be defined per board. The available
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@@ -191,7 +189,7 @@ int __hw_clock_source_init(uint32_t start_t)
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* doesn't appear to exist in either variant, and TIM9 cannot be triggered as a
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* slave from TIM4. We could perhaps use TIM9 as our fast counter on STM32L.
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*/
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#ifdef CHIP_VARIANT_stm32f100
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#ifndef CHIP_VARIANT_stm32l15x
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void watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
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{
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1
chip/stm32/jtag-stm32f10x.c
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1
chip/stm32/jtag-stm32f10x.c
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@@ -0,0 +1 @@
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jtag-stm32f100.c
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@@ -36,20 +36,25 @@
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#define STM32_IRQ_DMA_CHANNEL_5 15
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#define STM32_IRQ_DMA_CHANNEL_6 16
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#define STM32_IRQ_DMA_CHANNEL_7 17
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#define STM32_IRQ_ADC_1 18
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#define STM32_IRQ_ADC_1 18 /* ADC1 and ADC2 interrupt on STM32F10x */
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#define STM32_IRQ_USB_HP 19
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#define STM32_IRQ_CAN_TX 19 /* STM32F10x only */
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#define STM32_IRQ_USB_LP 20
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#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F10x only */
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#define STM32_IRQ_DAC 21
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#define STM32_IRQ_CAN_RX1 21 /* STM32F10x only */
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#define STM32_IRQ_COMP 22
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#define STM32_IRQ_CAN_SCE 22 /* STM32F10x only */
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#define STM32_IRQ_EXTI9_5 23
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#define STM32_IRQ_LCD 24 /* STM32L15X only */
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#define STM32_IRQ_TIM1_BRK_TIM15 24 /* STM32F100 only */
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#define STM32_IRQ_TIM1_BRK_TIM15 24 /* TIM15 interrupt on STM32F100 only */
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#define STM32_IRQ_TIM9 25 /* STM32L15X only */
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#define STM32_IRQ_TIM1_UP_TIM16 25 /* STM32F100 only */
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#define STM32_IRQ_TIM1_UP_TIM16 25 /* TIM16 interrupt on STM32F100 only */
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#define STM32_IRQ_TIM10 26 /* STM32L15X only */
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#define STM32_IRQ_TIM1_TRG_TIM17 26 /* STM32F100 only */
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#define STM32_IRQ_TIM1_TRG_COM 26 /* STM32F10x only */
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#define STM32_IRQ_TIM11 27 /* STM32L15X only */
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#define STM32_IRQ_TIM1_CC 27 /* STM32F100 only */
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#define STM32_IRQ_TIM1_CC 27 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_TIM2 28
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#define STM32_IRQ_TIM3 29
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#define STM32_IRQ_TIM4 30
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@@ -64,26 +69,31 @@
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#define STM32_IRQ_USART3 39
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#define STM32_IRQ_EXTI15_10 40
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#define STM32_IRQ_RTC_ALARM 41
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#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X only */
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#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
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#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
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#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X and STM32F10x */
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#define STM32_IRQ_CEC 42 /* STM32F100 only */
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#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
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#define STM32_IRQ_TIM12 43 /* STM32F100 only */
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#define STM32_IRQ_TIM8_BRK 43 /* STM32F10x only */
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#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
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#define STM32_IRQ_TIM13 44 /* STM32F100 only */
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#define STM32_IRQ_TIM8_UP 44 /* STM32F10x only */
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#define STM32_IRQ_TIM14 45 /* STM32F100 only */
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/* positions 46-47 are reserved on STM32 */
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#define STM32_IRQ_FSMC 48 /* STM32F100 only */
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/* position 49 is reserved on STM32 */
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#define STM32_IRQ_TIM5 50 /* STM32F100 only */
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#define STM32_IRQ_SPI3 51 /* STM32F100 only */
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#define STM32_IRQ_UART4 52 /* STM32F100 only */
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#define STM32_IRQ_UART5 53 /* STM32F100 only */
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#define STM32_IRQ_TIM8_TRG_COM 45 /* STM32F10x only */
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#define STM32_IRQ_TIM8_CC 46 /* STM32F10x only */
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#define STM32_IRQ_ADC3 47 /* STM32F10x only */
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#define STM32_IRQ_FSMC 48 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_SDIO 49 /* STM32F10x only */
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#define STM32_IRQ_TIM5 50 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_SPI3 51 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_UART4 52 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_UART5 53 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_TIM6_DAC 54 /* STM32F100 only */
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#define STM32_IRQ_TIM7 55 /* STM32F100 only */
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#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F100 only */
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#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F100 only */
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#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F100 only */
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#define STM32_IRQ_DMA2_CHANNEL4_5 59 /* STM32F100 only */
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#define STM32_IRQ_TIM6 54 /* STM32F10x only */
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#define STM32_IRQ_TIM7 55 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F100 and STM32F10x */
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#define STM32_IRQ_DMA2_CHANNEL4_5 59 /* STM32F100 and STM32F10x */
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/* if MISC_REMAP bits are set */
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#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F100 only */
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@@ -91,8 +101,8 @@
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#define STM32_USART1_BASE 0x40013800
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#define STM32_USART2_BASE 0x40004400
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#define STM32_USART3_BASE 0x40004800
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#define STM32_UART4_BASE 0x40004c00 /* STM32F100 only */
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#define STM32_UART5_BASE 0x40005000 /* STM32F100 only */
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#define STM32_UART4_BASE 0x40004c00 /* STM32F100 and STM32F10x */
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#define STM32_UART5_BASE 0x40005000 /* STM32F100 and STM32F10x */
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#define STM32_USART_BASE(n) STM32_CAT(STM32_USART, n, _BASE)
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@@ -110,19 +120,26 @@
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#define STM32_IRQ_USART(n) STM32_CAT(STM32_IRQ_USART, n, )
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/* --- TIMERS --- */
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#define STM32_TIM1_BASE 0x40012c00 /* STM32F100 only */
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#define STM32_TIM1_BASE 0x40012c00 /* STM32F100 and STM32F10x */
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#define STM32_TIM2_BASE 0x40000000
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#define STM32_TIM3_BASE 0x40000400
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#define STM32_TIM4_BASE 0x40000800
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#define STM32_TIM5_BASE 0x40000c00 /* STM32F100 only */
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#define STM32_TIM5_BASE 0x40000c00 /* STM32F100 and STM32F10x */
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#define STM32_TIM6_BASE 0x40001000
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#define STM32_TIM7_BASE 0x40001400
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#define STM32_TIM8_BASE 0x40013400 /* STM32F10x only */
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#if defined(CHIP_VARIANT_stm32l15x)
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#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */
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#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */
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#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */
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#define STM32_TIM12_BASE 0x40001800 /* STM32F100 only */
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#define STM32_TIM13_BASE 0x40001c00 /* STM32F100 only */
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#define STM32_TIM14_BASE 0x40002000 /* STM32F100 only */
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#elif defined(CHIP_VARIANT_stm32f10x)
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#define STM32_TIM9_BASE 0x40014C00 /* STM32F10x only */
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#define STM32_TIM10_BASE 0x40015000 /* STM32F10x only */
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#define STM32_TIM11_BASE 0x40015400 /* STM32F10x only */
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#endif /* TIM9-11 */
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#define STM32_TIM12_BASE 0x40001800 /* STM32F100 and STM32F10x */
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#define STM32_TIM13_BASE 0x40001c00 /* STM32F100 and STM32F10x */
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#define STM32_TIM14_BASE 0x40002000 /* STM32F100 and STM32F10x */
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#define STM32_TIM15_BASE 0x40014000 /* STM32F100 only */
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#define STM32_TIM16_BASE 0x40014400 /* STM32F100 only */
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#define STM32_TIM17_BASE 0x40014800 /* STM32F100 only */
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@@ -142,6 +159,7 @@
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#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24)
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#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28)
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#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C)
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#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30)
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#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34)
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#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38)
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#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C)
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@@ -208,7 +226,7 @@
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#define GPIO_ALT_RI 0xE
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#define GPIO_ALT_EVENTOUT 0xF
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#elif defined(CHIP_VARIANT_stm32f100)
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#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
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#define STM32_GPIOA_BASE 0x40010800
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#define STM32_GPIOB_BASE 0x40010c00
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#define STM32_GPIOC_BASE 0x40011000
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@@ -298,7 +316,7 @@
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#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
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#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
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#elif defined(CHIP_VARIANT_stm32f100)
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#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
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#define STM32_RCC_BASE 0x40021000
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#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
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@@ -311,7 +329,7 @@
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#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c)
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#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20)
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#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24)
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#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c)
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#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F100 */
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#define RCC_AHBENR_DMA1EN (1 << 0)
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@@ -360,7 +378,7 @@
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#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
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#define STM32_BKP_ENTRIES 20
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#elif defined(CHIP_VARIANT_stm32f100)
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#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
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#define STM32_RTC_CRH REG32(STM32_RTC_BASE + 0x00)
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#define STM32_RTC_CRL REG32(STM32_RTC_BASE + 0x04)
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#define STM32_RTC_PRLH REG32(STM32_RTC_BASE + 0x08)
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@@ -374,15 +392,22 @@
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/* --- Backup Registers --- */
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#define STM32_BKP_BASE 0x40006c00
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#define STM32_BKP_DATA(n) REG16(STM32_BKP_BASE + 4 + 4 * (n))
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#if defined(CHIP_VARIANT_stm32f10x)
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#define STM32_BKP_ENTRIES 42
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#define STM32_BKP_DATA(n) \
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REG16(STM32_BKP_BASE + (n < 11 ? 0x4 : 0x40) + 4 * (n))
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#else
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#define STM32_BKP_ENTRIES 10
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#define STM32_BKP_DATA(n) REG16(STM32_BKP_BASE + 0x4 + 4 * (n))
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#endif
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#define STM32_BKP_RTCCR REG16(STM32_BKP_BASE + 0x2c)
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#define STM32_BKP_CR REG16(STM32_BKP_BASE + 0x30)
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#define STM32_BKP_CSR REG16(STM32_BKP_BASE + 0x34)
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#define STM32_RTC_BACKUP(n) STM32_BKP_DATA(n)
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#define STM32_BKP_ENTRIES 10
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#else
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#error Unsupported chip variant
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#endif
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@@ -404,6 +429,8 @@ struct spi_ctlr {
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unsigned crcp;
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unsigned rxcrc;
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unsigned txcrc;
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unsigned i2scfgr; /* STM32F10x only */
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unsigned i2spr; /* STM32F10x only */
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};
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/*
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@@ -451,7 +478,7 @@ struct spi_ctlr {
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#define STM32_OPTB_COMPL_SHIFT 16
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#elif defined(CHIP_VARIANT_stm32f100)
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#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
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#define STM32_FLASH_REGS_BASE 0x40022000
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#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
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@@ -490,6 +517,8 @@ struct spi_ctlr {
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#define STM32_ADC1_BASE 0x40012400
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#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
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#define STM32_ADC2_BASE 0x40012800 /* STM32F10x only */
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#define STM32_ADC3_BASE 0x40013C00 /* STM32F10x only */
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#if defined(CHIP_VARIANT_stm32f100)
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#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
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@@ -519,7 +548,7 @@ struct spi_ctlr {
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#if defined(CHIP_VARIANT_stm32l15x)
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#define STM32_DMA1_BASE 0x40026000
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#define STM32_DMA2_BASE 0x40026400
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#elif defined(CHIP_VARIANT_stm32f100)
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#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
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#define STM32_DMA1_BASE 0x40020000
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/* FIXME: DMA2 is only available on high-density devices, but is used as part
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* of a sanity check in dma.c */
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@@ -528,4 +557,13 @@ struct spi_ctlr {
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#error Unsupported chip variant
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#endif
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#define STM32_FSMC_BASE 0xA0000000 /* STM32F10x only */
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#define STM32_USB_OTG_FS_BASE 0x50000000 /* STM32F10x only */
|
||||
#define STM32_ETHERNET_BASE 0x40028000 /* STM32F10x only */
|
||||
#define STM32_SDIO_BASE 0x40018000 /* STM32F10x only */
|
||||
#define STM32_BXCAN1_BASE 0x40006400 /* STM32F10x only */
|
||||
#define STM32_BXCAN2_BASE 0x40006800 /* STM32F10x only */
|
||||
#define STM32_USB_CAN_SRAM_BASE 0x40006000 /* STM32F10x only */
|
||||
#define STM32_USB_FS_BASE 0x40005C00 /* STM32F10x only */
|
||||
|
||||
#endif /* __STM32_REGISTERS */
|
||||
|
||||
@@ -130,7 +130,7 @@ void system_pre_init(void)
|
||||
/* Enable RTC and use LSI as clock source */
|
||||
STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
|
||||
}
|
||||
#elif defined(CHIP_VARIANT_stm32f100)
|
||||
#elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
|
||||
if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) {
|
||||
/* the RTC settings are bad, we need to reset it */
|
||||
STM32_RCC_BDCR |= 0x00010000;
|
||||
|
||||
Reference in New Issue
Block a user