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ec_chip_mchp: Add PWM and fan files
Add Microchip MEC17xx family PWM and fan source files for review BRANCH=none BUG= TEST=Review only. Change-Id: I91439ab999a4662d690b58b0fbbb887f643b3673 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
This commit is contained in:
Scott Worley
164
chip/mchp/fan.c
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164
chip/mchp/fan.c
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MCHP MEC fan control module. */
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/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
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#include "fan.h"
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#include "registers.h"
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#include "util.h"
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#include "tfdp_chip.h"
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/* Maximum tach reading/target value */
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#define MAX_TACH 0x1fff
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/* Tach target value for disable fan */
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#define FAN_OFF_TACH 0xfff8
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/*
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* RPM = (n - 1) * m * f * 60 / poles / TACH
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* n = number of edges = 5
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* m = multiplier defined by RANGE = 2 in our case
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* f = 32.768K
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* poles = 2
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*/
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#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
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#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
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static int rpm_setting;
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static int duty_setting;
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static int in_rpm_mode = 1;
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static void clear_status(void)
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{
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/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
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MCHP_FAN_STATUS(0) = 0x23;
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}
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void fan_set_enabled(int ch, int enabled)
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{
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if (in_rpm_mode) {
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if (enabled)
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fan_set_rpm_target(ch, rpm_setting);
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else
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MCHP_FAN_TARGET(0) = FAN_OFF_TACH;
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} else {
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if (enabled)
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fan_set_duty(ch, duty_setting);
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else
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MCHP_FAN_SETTING(0) = 0;
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}
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clear_status();
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}
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int fan_get_enabled(int ch)
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{
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if (in_rpm_mode)
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return (MCHP_FAN_TARGET(0) & 0xff00) != 0xff00;
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else
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return !!MCHP_FAN_SETTING(0);
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}
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void fan_set_duty(int ch, int percent)
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{
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if (percent < 0)
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percent = 0;
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else if (percent > 100)
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percent = 100;
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duty_setting = percent;
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MCHP_FAN_SETTING(0) = percent * 255 / 100;
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clear_status();
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}
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int fan_get_duty(int ch)
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{
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return duty_setting;
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}
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int fan_get_rpm_mode(int ch)
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{
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return !!(MCHP_FAN_CFG1(0) & (1 << 7));
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}
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void fan_set_rpm_mode(int ch, int rpm_mode)
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{
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if (rpm_mode)
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MCHP_FAN_CFG1(0) |= 1 << 7;
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else
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MCHP_FAN_CFG1(0) &= ~(1 << 7);
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clear_status();
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}
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int fan_get_rpm_actual(int ch)
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{
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if ((MCHP_FAN_READING(0) >> 8) == 0xff)
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return 0;
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else
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return TACH_TO_RPM(MCHP_FAN_READING(0) >> 3);
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}
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int fan_get_rpm_target(int ch)
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{
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return rpm_setting;
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}
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void fan_set_rpm_target(int ch, int rpm)
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{
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rpm_setting = rpm;
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MCHP_FAN_TARGET(0) = RPM_TO_TACH(rpm) << 3;
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clear_status();
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}
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enum fan_status fan_get_status(int ch)
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{
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uint8_t sts = MCHP_FAN_STATUS(0);
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if (sts & ((1 << 5) | (1 << 1)))
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return FAN_STATUS_FRUSTRATED;
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if (fan_get_rpm_actual(ch) == 0)
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return FAN_STATUS_STOPPED;
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return FAN_STATUS_LOCKED;
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}
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int fan_is_stalled(int ch)
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{
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uint8_t sts = MCHP_FAN_STATUS(0);
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if (fan_get_rpm_actual(ch)) {
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MCHP_FAN_STATUS(0) = 0x1;
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return 0;
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}
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return sts & 0x1;
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}
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void fan_channel_setup(int ch, unsigned int flags)
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{
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/* Clear PCR sleep enable for RPM2FAN0 */
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MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_RPMPWM0);
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/*
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* Fan configuration 1 register:
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* 0x80 = bit 7 = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
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* 0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
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* 0x08 = bits 4:3 = 5 edges, 2 poles
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* 0x03 = bits 2:0 = 400 ms update time
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*
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* Fan configuration 2 register:
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* 0x00 = bit 6 = Ramp control disabled
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* 0x00 = bit 5 = Glitch filter enabled
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* 0x18 = bits 4:3 = Using both derivative options
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* 0x02 = bits 2:1 = error range is 50 RPM
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* 0x00 = bits 0 = normal polarity
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*/
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if (flags & FAN_USE_RPM_MODE)
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MCHP_FAN_CFG1(0) = 0xab;
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else
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MCHP_FAN_CFG1(0) = 0x2b;
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MCHP_FAN_CFG2(0) = 0x1a;
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clear_status();
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}
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155
chip/mchp/pwm.c
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155
chip/mchp/pwm.c
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@@ -0,0 +1,155 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* PWM control module for MCHP MEC family */
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "pwm.h"
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#include "pwm_chip.h"
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#include "registers.h"
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#include "util.h"
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#include "tfdp_chip.h"
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#define CPUTS(outstr) cputs(CC_PWM, outstr)
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#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
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/*
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* PWMs that must remain active in low-power idle -
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* PWM 0,1-8 are b[4,20:27] of MCHP_PCR_SLP_EN1
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* PWM 9 is b[31] of MCHP_PCR_SLP_EN3
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* PWM 10 - 11 are b[0:1] of MCHP_PCR_SLP_EN4
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* store 32-bit word with
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* b[0:1] = PWM 10-11
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* b[4,20:27] = PWM 0, 1-8
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* b[31] = PWM 9
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*/
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static uint32_t pwm_keep_awake_mask;
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const uint8_t pwm_slp_bitpos[12] = {
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4, 20, 21, 22, 23, 24, 25, 26, 27, 31, 0, 1
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};
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static uint32_t pwm_get_sleep_mask(int id)
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{
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uint32_t bitpos = 32;
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if (id < 12)
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bitpos = (uint32_t)pwm_slp_bitpos[id];
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return (1ul << bitpos);
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}
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void pwm_enable(enum pwm_channel ch, int enabled)
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{
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int id = pwm_channels[ch].channel;
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uint32_t pwm_slp_mask;
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pwm_slp_mask = pwm_get_sleep_mask(id);
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if (enabled) {
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MCHP_PWM_CFG(id) |= 0x1;
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if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
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pwm_keep_awake_mask |= pwm_slp_mask;
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} else {
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MCHP_PWM_CFG(id) &= ~0x1;
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pwm_keep_awake_mask &= ~pwm_slp_mask;
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}
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}
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int pwm_get_enabled(enum pwm_channel ch)
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{
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return MCHP_PWM_CFG(pwm_channels[ch].channel) & 0x1;
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}
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void pwm_set_duty(enum pwm_channel ch, int percent)
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{
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int id = pwm_channels[ch].channel;
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if (percent < 0)
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percent = 0;
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else if (percent > 100)
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percent = 100;
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MCHP_PWM_ON(id) = percent;
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MCHP_PWM_OFF(id) = 100 - percent;
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}
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int pwm_get_duty(enum pwm_channel ch)
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{
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return MCHP_PWM_ON(pwm_channels[ch].channel);
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}
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void pwm_keep_awake(void)
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{
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if (pwm_keep_awake_mask) {
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/* b[4,20:27] */
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MCHP_PCR_SLP_EN1 &= ~(pwm_keep_awake_mask &
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(MCHP_PCR_SLP_EN1_PWM_ALL));
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/* b[31] */
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MCHP_PCR_SLP_EN3 &= ~(pwm_keep_awake_mask &
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(MCHP_PCR_SLP_EN3_PWM_ALL));
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/* b[1:0] */
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MCHP_PCR_SLP_EN4 &= ~(pwm_keep_awake_mask &
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(MCHP_PCR_SLP_EN4_PWM_ALL));
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} else {
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MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
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}
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}
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static void pwm_configure(int ch, int active_low, int clock_low)
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{
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/*
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* clock_low=0 selects the 48MHz Ring Oscillator source
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* clock_low=1 selects the 100kHz_Clk source
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*/
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MCHP_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */
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(active_low ? (1 << 2) : 0) |
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(clock_low ? (1 << 1) : 0);
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}
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static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = {
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MCHP_PCR_PWM0,
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MCHP_PCR_PWM1,
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MCHP_PCR_PWM2,
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MCHP_PCR_PWM3,
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MCHP_PCR_PWM4,
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MCHP_PCR_PWM5,
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MCHP_PCR_PWM6,
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MCHP_PCR_PWM7,
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MCHP_PCR_PWM8,
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MCHP_PCR_PWM9,
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MCHP_PCR_PWM10,
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MCHP_PCR_PWM11,
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};
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static void pwm_slp_en(int pwm_id, int sleep_en)
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{
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if ((pwm_id < 0) || (pwm_id > MCHP_PWM_ID_MAX))
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return;
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if (sleep_en)
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MCHP_PCR_SLP_EN_DEV(pwm_pcr[pwm_id]);
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else
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MCHP_PCR_SLP_DIS_DEV(pwm_pcr[pwm_id]);
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}
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static void pwm_init(void)
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{
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int i;
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for (i = 0; i < PWM_CH_COUNT; ++i) {
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pwm_slp_en(pwm_channels[i].channel, 0);
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pwm_configure(pwm_channels[i].channel,
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pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
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pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
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pwm_set_duty(i, 0);
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}
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}
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DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_DEFAULT);
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23
chip/mchp/pwm_chip.h
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23
chip/mchp/pwm_chip.h
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@@ -0,0 +1,23 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MEC1701H-specific PWM module for Chrome EC */
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#ifndef __CROS_EC_PWM_CHIP_H
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#define __CROS_EC_PWM_CHIP_H
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/* Data structure to define PWM channels. */
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struct pwm_t {
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/* PWM Channel ID */
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int channel;
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/* PWM channel flags. See include/pwm.h */
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uint32_t flags;
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};
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extern const struct pwm_t pwm_channels[];
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void pwm_keep_awake(void);
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#endif /* __CROS_EC_PWM_CHIP_H */
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