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util: ecst: Add support for npcx7 series.

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ecst adds the support for npcx7 series in this CL. (The name of npcx7m6f
is fixed. The others are TBD.) It also includes:
1. Fix few typos and replace tab with spaces in ecst.h for better
   alignment.
2. Add -spiclkratio parameter for the ratio between core and spi flash
   clock in npcx7. (default ratio is 1.)
3. Add -unlimburst parameter for burst mode of spi flash accesses.
   (default is disable)

BRANCH=none
BUG=none
TEST=No build errors for npcx7 and npcx5 series. Build poppy board with
ecst 1.0.3 and upload FW to platfomr. No sympton found.

Change-Id: I004edc068c6496390e03d8ee5e39e4f23e4b835f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/476413
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Mulin Chao
2017-04-13 13:37:44 +08:00
committed by chrome-bot
parent 81596da3d0
commit eca98d30ff
2 changed files with 343 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files

278
util/ecst.c
View File

@@ -30,10 +30,15 @@ int is_ptr_merge;
unsigned int g_ram_start_address;
unsigned int g_ram_size;
unsigned int api_file_size_bytes;
int is_mrider15 = FALSE;
/* Chips information, RAM start address and RAM size. */
struct chip_info chip_info[] = {{NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE},
{NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE} };
{NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE},
{NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE},
{NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE},
{NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE},};
static unsigned int calc_api_csum_bin(void);
static unsigned int initialize_crc_32(void);
@@ -66,7 +71,8 @@ int main(int argc, char *argv[])
/* Following variables: common to all modes */
int main_status = TRUE;
unsigned int main_temp = 0L;
char main_str_temp[TMP_STR_SIZE];
char main_str_temp[TMP_STR_SIZE];
char *end_ptr;
int arg_num;
int arg_ind;
@@ -77,6 +83,7 @@ int main(int argc, char *argv[])
/* Following variables are used when bin file is provided */
struct tbinparams bin_params;
bin_params.bin_params = 0;
input_file_name[0] = '\0';
@@ -91,17 +98,18 @@ int main(int argc, char *argv[])
/* Initialize Global variables */
g_verbose = NO_VERBOSE;
g_ram_start_address = chip_info[NPCX5M5G].ram_addr;
g_ram_size = chip_info[NPCX5M5G].ram_size;
g_ram_start_address = chip_info[DEFAULT_CHIP].ram_addr;
g_ram_size = chip_info[DEFAULT_CHIP].ram_size;
/* Set default values */
g_calc_type = CALC_TYPE_NONE;
bin_params.spi_max_clk = SPI_MAX_CLOCK_DEFAULT;
bin_params.spi_clk_ratio = 0x00;
bin_params.spi_read_mode = SPI_READ_MODE_DEFAULT;
bin_params.fw_load_addr =
chip_info[NPCX5M5G].ram_addr;
chip_info[DEFAULT_CHIP].ram_addr;
bin_params.fw_ep =
chip_info[NPCX5M5G].ram_addr;
chip_info[DEFAULT_CHIP].ram_addr;
bin_params.fw_err_detec_s_addr = FW_CRC_START_ADDR;
bin_params.fw_err_detec_e_addr = FW_CRC_START_ADDR;
bin_params.flash_size = FLASH_SIZE_DEFAULT;
@@ -182,10 +190,65 @@ int main(int argc, char *argv[])
"%s",
main_str_temp) != 1)) {
my_printf(TERR, "\nCannot read chip name, ");
my_printf(TERR, "npcx5m5g or npcx5m6g.\n");
my_printf(TERR, "npcx7m7k, npcx7m6f, npcx7m5g");
my_printf(TERR, ", npcx5m5g or npcx5m6g.\n");
main_status = FALSE;
} else {
if (str_cmp_no_case(main_str_temp,
"npcx7m7k") == 0) {
if ((bin_params.bin_params
& BIN_FW_LOAD_START_ADDR) ==
0x00000000)
bin_params.fw_load_addr =
chip_info[NPCX7M7].ram_addr;
if ((bin_params.bin_params
& BIN_FW_ENTRY_POINT) ==
0x00000000)
bin_params.fw_ep =
chip_info[NPCX7M7].ram_addr;
g_ram_start_address =
chip_info[NPCX7M7].ram_addr;
g_ram_size =
chip_info[NPCX7M7].ram_size;
} else if (str_cmp_no_case(main_str_temp,
"npcx7m6f") == 0) {
if ((bin_params.bin_params
& BIN_FW_LOAD_START_ADDR) ==
0x00000000)
bin_params.fw_load_addr =
chip_info[NPCX7M6].ram_addr;
if ((bin_params.bin_params &
BIN_FW_ENTRY_POINT) ==
0x00000000)
bin_params.fw_ep =
chip_info[NPCX7M6].ram_addr;
g_ram_start_address =
chip_info[NPCX7M6].ram_addr;
g_ram_size =
chip_info[NPCX7M6].ram_size;
} else if (str_cmp_no_case(main_str_temp,
"npcx7m5g") == 0) {
if ((bin_params.bin_params
& BIN_FW_LOAD_START_ADDR) ==
0x00000000)
bin_params.fw_load_addr =
chip_info[NPCX7M5].ram_addr;
if ((bin_params.bin_params &
BIN_FW_ENTRY_POINT) ==
0x00000000)
bin_params.fw_ep =
chip_info[NPCX7M5].ram_addr;
g_ram_start_address =
chip_info[NPCX7M5].ram_addr;
g_ram_size =
chip_info[NPCX7M5].ram_size;
} else if (str_cmp_no_case(main_str_temp,
"npcx5m5g") == 0) {
if ((bin_params.bin_params
& BIN_FW_LOAD_START_ADDR) ==
@@ -202,6 +265,9 @@ int main(int argc, char *argv[])
chip_info[NPCX5M5G].ram_addr;
g_ram_size =
chip_info[NPCX5M5G].ram_size;
is_mrider15 = TRUE;
} else if (str_cmp_no_case(main_str_temp,
"npcx5m6g") == 0) {
if ((bin_params.bin_params &
@@ -221,13 +287,17 @@ int main(int argc, char *argv[])
g_ram_size =
chip_info[NPCX5M6G].ram_size;
is_mrider15 = TRUE;
} else {
my_printf(TERR,
"\nInvalid chip name (%s) ",
main_str_temp);
my_printf(TERR, "should be npcx5m5g ");
my_printf(TERR, "or npcx5m6g.\n");
main_status = FALSE;
my_printf(TERR, "should be npcx7m7k, ");
my_printf(TERR, "npcx7m6f, npcx7m5g, ");
my_printf(TERR, "npcx5m5g or ");
my_printf(TERR, "npcx5m6g.");
main_status = FALSE;
}
}
@@ -339,7 +409,7 @@ int main(int argc, char *argv[])
arg_ind++;
bin_params.fw_hdr_offset = main_temp;
}
/* -spimacclk Get SPI flash mac clock. */
/* -spimaxclk Get SPI flash max clock. */
} else if (str_cmp_no_case(hdr_args[arg_ind],
"-spimaxclk") == 0) {
arg_ind++;
@@ -351,8 +421,22 @@ int main(int argc, char *argv[])
main_status = FALSE;
} else
bin_params.spi_max_clk =
(unsigned char) main_temp;
/* -spiclkratio Get SPI flash max clock ratio. */
} else if (str_cmp_no_case(hdr_args[arg_ind],
"-spiclkratio") == 0) {
arg_ind++;
if ((hdr_args[arg_ind] == NULL) ||
(sscanf(hdr_args[arg_ind],
"%d", &main_temp) != 1)) {
my_printf(TERR,
"\nCannot read SPI Clock Ratio\n");
main_status = FALSE;
} else
bin_params.spi_clk_ratio =
(unsigned char)main_temp;
/* spireadmode get SPI read mode. */
/* spireadmode get SPI read mode. */
} else if (str_cmp_no_case(hdr_args[arg_ind],
"-spireadmode") == 0) {
arg_ind++;
@@ -385,18 +469,25 @@ int main(int argc, char *argv[])
SPI_QUAD_MODE;
else {
my_printf(TERR,
"\nInvalid SPI Flash Read "
"Mode (%s), it should be "
"normal, singleMode, "
"dualMode or quadMode !\n",
"\nInvalid SPI Flash Read ");
my_printf(TERR,
"Mode (%s), it should be ",
main_str_temp);
my_printf(TERR,
"normal, singleMode, ");
my_printf(TERR,
"dualMode or quadMode !\n");
main_status = FALSE;
}
}
/* -nofcrc disable FW CRC. */
} else if (str_cmp_no_case(hdr_args[arg_ind], "-nofcrc") == 0)
bin_params.bin_params |=
BIN_FW_CRC_DISABLE;
}
/* -unlimburst enable unlimited burst */
else if (str_cmp_no_case(hdr_args[arg_ind], "-unlimburst") == 0)
bin_params.bin_params |= BIN_UNLIM_BURST_ENABLE;
/* -nofcrc disable FW CRC. */
else if (str_cmp_no_case(hdr_args[arg_ind], "-nofcrc") == 0)
bin_params.bin_params |= BIN_FW_CRC_DISABLE;
/* -fwloadaddr, Get the FW load address. */
else if (str_cmp_no_case(hdr_args[arg_ind],
@@ -414,10 +505,12 @@ int main(int argc, char *argv[])
if ((main_temp &
ADDR_16_BYTES_ALIGNED_MASK) != 0) {
my_printf(TERR,
"\nFW load address start "
"address (0x%08X) is not "
"16-bytes aligned !\n",
"\nFW load address start ");
my_printf(TERR,
"address (0x%08X) is not ",
main_temp);
my_printf(TERR,
"16-bytes aligned !\n");
main_status = FALSE;
} else {
bin_params.fw_load_addr =
@@ -431,7 +524,8 @@ int main(int argc, char *argv[])
if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET)
!= 0x00000000) {
my_printf(TERR,
"\n-fwep not allowed, FW entry point"
"\n-fwep not allowed, FW entry point");
my_printf(TERR,
" already set using -usearmrst!\n");
main_status = FALSE;
} else {
@@ -462,7 +556,8 @@ int main(int argc, char *argv[])
"%x",
&main_temp) != 1)) {
my_printf(TERR,
"\nCannot read FW CRC"
"\nCannot read FW CRC");
my_printf(TERR,
" start address !\n");
main_status = FALSE;
} else {
@@ -478,11 +573,16 @@ int main(int argc, char *argv[])
} else if (str_cmp_no_case(hdr_args[arg_ind],
"-crcsize") == 0) {
arg_ind++;
if ((hdr_args[arg_ind] == NULL) ||
(sscanf(hdr_args[arg_ind], "%x", &main_temp)
!= 1)) {
my_printf(TERR, "\nCannot read FW CRC ");
my_printf(TERR, "\area size !\n");
main_temp = 0x00;
if (hdr_args[arg_ind] == NULL)
end_ptr = NULL;
else
main_temp = strtol(hdr_args[arg_ind],
&end_ptr, 16);
if (hdr_args[arg_ind] == end_ptr) {
my_printf(TERR,
"\nCannot read FW CRC area size !\n");
main_status = FALSE;
} else {
bin_params.fw_err_detec_e_addr =
@@ -566,7 +666,8 @@ int main(int argc, char *argv[])
if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
!= 0) {
my_printf(TERR,
"\nFW Image address (0x%08X)"
"\nFW Image address (0x%08X)");
my_printf(TERR,
" isn't 16-bytes aligned !\n",
main_temp);
main_status = FALSE;
@@ -591,9 +692,14 @@ int main(int argc, char *argv[])
/* -bhoffset, BootLoader Header Offset (BH location in BT). */
else if (str_cmp_no_case(hdr_args[arg_ind], "-bhoffset") == 0) {
arg_ind++;
if ((hdr_args[arg_ind] == NULL) ||
(sscanf(hdr_args[arg_ind], "%x", &main_temp)
!= 1)) {
main_temp = 0x00;
if (hdr_args[arg_ind] == NULL)
end_ptr = NULL;
else
main_temp = strtol(hdr_args[arg_ind],
&end_ptr, 16);
if (hdr_args[arg_ind] == end_ptr) {
my_printf(TERR, "\nCannot read BootLoader");
my_printf(TERR, " Header Offset !\n");
main_status = FALSE;
@@ -602,18 +708,20 @@ int main(int argc, char *argv[])
if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
!= 0) {
my_printf(TERR,
"\nFW Image address (0x%08X) "
"is not 16-bytes aligned !\n",
"\nFW Image address (0x%08X) ",
main_temp);
main_status = FALSE;
my_printf(TERR,
"is not 16-bytes aligned!\n");
}
if (main_temp > MAX_FLASH_SIZE) {
my_printf(TERR,
"\nFW Image address (0x%08X)"
" is higher from flash size "
"(0x%08X) !\n",
main_temp,
"\nFW Image address (0x%08X)",
main_temp);
my_printf(TERR,
" is higher from flash size");
my_printf(TERR,
" (0x%08X) !\n",
MAX_FLASH_SIZE);
main_status = FALSE;
} else {
@@ -727,7 +835,8 @@ void exit_with_usage(void)
my_printf(TUSG, "\n -argfile <filename> - Arguments file name; ");
my_printf(TUSG, "includes multiple flags");
my_printf(TUSG, "\n -chip <name> - EC Chip Name: ");
my_printf(TUSG, "npcx5m5g|npcx5m6g (default is npcx5m5g)");
my_printf(TUSG, "npcx7m7k|npcx7m6f|npcx7m5g|npcx5m5g|npcx5m6g");
my_printf(TUSG, " (default is npcx5m5g)");
my_printf(TUSG, "\n -v - Verbose; prints ");
my_printf(TUSG, "information messages");
my_printf(TUSG, "\n -vv - Super Verbose; prints ");
@@ -741,8 +850,16 @@ void exit_with_usage(void)
my_printf(TUSG, "(default is ON)");
my_printf(TUSG, "\n -spimaxclk <val> - SPI Flash Maximum Clock, in");
my_printf(TUSG, " MHz: 20|25|33|40|50 (default is 20)");
my_printf(TUSG, "\n -spiclkratio <val> - Core Clock / SPI Flash ");
my_printf(TUSG, "Clocks Ratio: 1 | 2 (default is 1)");
my_printf(TUSG, "\n ");
my_printf(TUSG, "Note: Not relevant for npcx5mng chips family");
my_printf(TUSG, "\n -spireadmode <type> - SPI Flash Read Mode: ");
my_printf(TUSG, "normal|fast|dual|quad (default is normal)");
my_printf(TUSG, "\n -unlimburst - Enable FIU Unlimited ");
my_printf(TUSG, "\n ");
my_printf(TUSG, "Note: Not relevant for npcx5mng chips family");
my_printf(TUSG, "Burst for SPI Flash Accesses (default is disable).");
my_printf(TUSG, "\n -fwloadaddr <addr> - Firmware load start ");
my_printf(TUSG, "address (default is Start-of-RAM)");
my_printf(TUSG, "\n Located in code RAM, ");
@@ -868,22 +985,17 @@ int copy_file_to_file(char *dst_file_name,
*/
void my_printf(int error_level, char *fmt, ...)
{
char buffer[256];
va_list argptr;
va_start(argptr, fmt);
vsprintf(buffer, fmt, argptr);
va_end(argptr);
if ((g_verbose == NO_VERBOSE) && (error_level == TINF))
return;
if ((error_level == TDBG) && (g_verbose != SUPER_VERBOSE))
if ((g_verbose != SUPER_VERBOSE) && (error_level == TDBG))
return;
if (error_level == TERR)
fprintf(stderr, "%s", buffer);
else
printf("%s", buffer);
va_start(argptr, fmt);
vprintf(fmt, argptr);
va_end(argptr);
}
/*
@@ -1004,7 +1116,6 @@ int read_from_file(unsigned int offset,
my_printf(TERR, "\nIn read_from_file - %s", print_string);
my_printf(TERR, "\n\nInvalid call to read_from_file\n\n");
return FALSE;
break;
}
my_printf(TINF, "\nIn read_from_file - %s", print_string);
@@ -1201,12 +1312,12 @@ int main_bin(struct tbinparams binary_params)
if (((int)binary_params.fw_hdr_offset < 0) ||
(binary_params.fw_hdr_offset > bin_file_size_bytes)) {
my_printf(TERR,
"\nFW header offset 0x%08x (%d) should be in the"
"\nFW header offset 0x%08x (%d) should be in the",
binary_params.fw_hdr_offset);
my_printf(TERR,
" range of 0 and file size (%d).\n",
binary_params.fw_hdr_offset,
binary_params.fw_hdr_offset,
bin_file_size_bytes);
return FALSE;
bin_file_size_bytes); return FALSE;
}
/* Get the input directory and input file name. */
@@ -1286,7 +1397,36 @@ int main_bin(struct tbinparams binary_params)
binary_params.spi_max_clk);
my_printf(TERR, "- it should be 20, 25, 33, 40 or 50 MHz");
return FALSE;
}
/* If SPI clock ratio set for MRIDER15, then it is error. */
if ((binary_params.spi_clk_ratio != 0x00) && (is_mrider15 == TRUE)) {
my_printf(TERR, "\nspiclkratio is not relevant for");
my_printf(TERR, " npcx5mng chips family !\n");
return FALSE;
}
/*
* In case SPIU clock ratio didn't set by the user,
* set it to its default value.
*/
if (binary_params.spi_clk_ratio == 0x00)
binary_params.spi_clk_ratio = SPI_CLOCK_RATIO_1_VAL;
switch (binary_params.spi_clk_ratio) {
case SPI_CLOCK_RATIO_1_VAL:
tmp_param &= SPI_CLOCK_RATIO_1;
break;
case SPI_CLOCK_RATIO_2_VAL:
tmp_param |= SPI_CLOCK_RATIO_2;
break;
default:
my_printf(TERR, "\n\nInvalid SPI Core Clock Ratio (%d) ",
binary_params.spi_clk_ratio);
my_printf(TERR, "- it should be 1 or 2");
return FALSE;
}
if (!write_to_file(tmp_param, HDR_SPI_MAX_CLK_OFFSET, 1,
@@ -1294,7 +1434,20 @@ int main_bin(struct tbinparams binary_params)
return FALSE;
/* Write the SPI flash Read Mode. */
if (!write_to_file(binary_params.spi_read_mode,
tmp_param = binary_params.spi_read_mode;
/* If needed, set the unlimited burst bit. */
if (binary_params.bin_params & BIN_UNLIM_BURST_ENABLE) {
if (is_mrider15 == TRUE) {
my_printf(TERR, "\nunlimburst is not relevant for");
my_printf(TERR, " npcx5mng chips family !\n");
return FALSE;
}
tmp_param |= SPI_UNLIMITED_BURST_ENABLE;
}
if (!write_to_file(tmp_param,
HDR_SPI_READ_MODE_OFFSET, 1,
"HDR - SPI flash Read Mode "))
return FALSE;
@@ -1319,11 +1472,13 @@ int main_bin(struct tbinparams binary_params)
(g_ram_start_address + g_ram_size)) ||
(binary_params.fw_load_addr < g_ram_start_address)) {
my_printf(TERR,
"\nFW load address (0x%08x) should be between "
"\nFW load address (0x%08x) should be between ",
binary_params.fw_load_addr);
my_printf(TERR,
"start (0x%08x) and end (0x%08x) of RAM ).",
binary_params.fw_load_addr,
g_ram_start_address,
(g_ram_start_address + g_ram_size));
return FALSE;
}
@@ -1443,8 +1598,8 @@ int main_bin(struct tbinparams binary_params)
binary_params.fw_err_detec_e_addr);
my_printf(TERR,
"than the FW length %d (0x%08x)",
(binary_params.fw_len - 1),
(binary_params.fw_len - 1));
(binary_params.fw_len),
(binary_params.fw_len));
return FALSE;
}
}
@@ -1549,7 +1704,6 @@ int main_bin(struct tbinparams binary_params)
binary_params.flash_size);
my_printf(TERR, " it should be 1, 2, 4, 8 or 16 MBytes\n");
return FALSE;
break;
}
if (!write_to_file(tmp_param,
HDR_FLASH_SIZE_OFFSET,

233
util/ecst.h
View File

@@ -22,145 +22,165 @@
--------------------------------------------------------------------------*/
/* For the beauty */
#define TRUE 1
#define FALSE 0
#define TRUE 1
#define FALSE 0
/* CHANGEME when the version is updated */
#define T_VER 1
#define T_REV_MAJOR 0
#define T_REV_MINOR 1
#define T_VER 1
#define T_REV_MAJOR 0
#define T_REV_MINOR 3
/* Header starts by default at 0x20000 */
#define FIRMWARE_OFFSET_FROM_HEADER 0x40
#define FIRMWARE_OFFSET_FROM_HEADER 0x40
#define ARM_FW_ENTRY_POINT_OFFSET 0x04
#define ARM_FW_ENTRY_POINT_OFFSET 0x04
/* Some useful offsets inside the header */
#define HDR_ANCHOR_OFFSET 0
#define HDR_EXTENDED_ANCHOR_OFFSET 4
#define HDR_SPI_MAX_CLK_OFFSET 6
#define HDR_SPI_READ_MODE_OFFSET 7
#define HDR_ERR_DETECTION_CONF_OFFSET 8
#define HDR_FW_LOAD_START_ADDR_OFFSET 9
#define HDR_FW_ENTRY_POINT_OFFSET 13
#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17
#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21
#define HDR_FW_LENGTH_OFFSET 25
#define HDR_FLASH_SIZE_OFFSET 29
#define HDR_RESERVED 30
#define HDR_FW_HEADER_SIG_OFFSET 56
#define HDR_FW_IMAGE_SIG_OFFSET 60
#define HDR_ANCHOR_OFFSET 0
#define HDR_EXTENDED_ANCHOR_OFFSET 4
#define HDR_SPI_MAX_CLK_OFFSET 6
#define HDR_SPI_READ_MODE_OFFSET 7
#define HDR_ERR_DETECTION_CONF_OFFSET 8
#define HDR_FW_LOAD_START_ADDR_OFFSET 9
#define HDR_FW_ENTRY_POINT_OFFSET 13
#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17
#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21
#define HDR_FW_LENGTH_OFFSET 25
#define HDR_FLASH_SIZE_OFFSET 29
#define HDR_RESERVED 30
#define HDR_FW_HEADER_SIG_OFFSET 56
#define HDR_FW_IMAGE_SIG_OFFSET 60
#define FIRMW_CKSM_OFFSET 0x3C
#define FIRMW_CKSM_OFFSET 0x3C
/* Header field known values */
#define FW_HDR_ANCHOR 0x2A3B4D5E
#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E
#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1
#define FW_CRC_DISABLE 0x00
#define FW_CRC_ENABLE 0x02
#define HEADER_CRC_FIELDS_SIZE 8
#define FW_HDR_ANCHOR 0x2A3B4D5E
#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E
#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1
#define FW_CRC_DISABLE 0x00
#define FW_CRC_ENABLE 0x02
#define HEADER_CRC_FIELDS_SIZE 8
#define HDR_PTR_SIGNATURE 0x55AA650E
#define HDR_PTR_SIGNATURE 0x55AA650E
#define CKSMCRC_INV_BIT_OFFSET 0x1
#define CKSMCRC_INV_BIT_OFFSET 0x1
/* Some common Sizes */
#define STR_SIZE 200
#define ARG_SIZE 100
#define NAME_SIZE 160
#define BUFF_SIZE 0x400
#define HEADER_SIZE 64
#define TMP_STR_SIZE 20
#define PAD_VALUE 0x00
#define STR_SIZE 200
#define ARG_SIZE 100
#define NAME_SIZE 160
#define BUFF_SIZE 0x400
#define HEADER_SIZE 64
#define TMP_STR_SIZE 20
#define PAD_VALUE 0x00
#define MAX_ARGS 100
#define MAX_ARGS 100
/* Text Colors */
#define TDBG 0x02 /* Dark Green */
#define TPAS 0x0A /* light green */
#define TINF 0x0B /* light turquise */
#define TERR 0x0C /* light red */
#define TUSG 0x0E /* light yellow */
#define TDBG 0x02 /* Dark Green */
#define TPAS 0x0A /* light green */
#define TINF 0x0B /* light turquise */
#define TERR 0x0C /* light red */
#define TUSG 0x0E /* light yellow */
/* Indicates bin Command line parameters */
#define BIN_FW_HDR_CRC_DISABLE 0x0001
#define BIN_FW_CRC_DISABLE 0x0002
#define BIN_FW_START 0x0004
#define BIN_FW_SIZE 0x0008
#define BIN_CK_FIRMWARE 0x0010
#define BIN_FW_CKS_START 0x0020
#define BIN_FW_CKS_SIZE 0x0040
#define BIN_FW_CHANGE_SIG 0x0080
#define BIN_FW_SPI_MAX_CLK 0x0100
#define BIN_FW_LOAD_START_ADDR 0x0200
#define BIN_FW_ENTRY_POINT 0x0400
#define BIN_FW_LENGTH 0x0800
#define BIN_FW_HDR_OFFSET 0x1000
#define BIN_FW_USER_ARM_RESET 0x2000
#define BIN_FW_HDR_CRC_DISABLE 0x0001
#define BIN_FW_CRC_DISABLE 0x0002
#define BIN_FW_START 0x0004
#define BIN_FW_SIZE 0x0008
#define BIN_CK_FIRMWARE 0x0010
#define BIN_FW_CKS_START 0x0020
#define BIN_FW_CKS_SIZE 0x0040
#define BIN_FW_CHANGE_SIG 0x0080
#define BIN_FW_SPI_MAX_CLK 0x0100
#define BIN_FW_LOAD_START_ADDR 0x0200
#define BIN_FW_ENTRY_POINT 0x0400
#define BIN_FW_LENGTH 0x0800
#define BIN_FW_HDR_OFFSET 0x1000
#define BIN_FW_USER_ARM_RESET 0x2000
#define BIN_UNLIM_BURST_ENABLE 0x4000
#define ECRP_OFFSET 0x01
#define ECRP_INPUT_FILE 0x02
#define ECRP_OUTPUT_FILE 0x04
#define ECRP_OFFSET 0x01
#define ECRP_INPUT_FILE 0x02
#define ECRP_OUTPUT_FILE 0x04
#define DIR_DELIMITER_STR "/"
#define DIR_DELIMITER_STR "/"
#define SPI_MAX_CLOCK_20_MHZ_VAL 20
#define SPI_MAX_CLOCK_25_MHZ_VAL 25
#define SPI_MAX_CLOCK_33_MHZ_VAL 33
#define SPI_MAX_CLOCK_40_MHZ_VAL 40
#define SPI_MAX_CLOCK_50_MHZ_VAL 50
#define SPI_MAX_CLOCK_20_MHZ_VAL 20
#define SPI_MAX_CLOCK_25_MHZ_VAL 25
#define SPI_MAX_CLOCK_33_MHZ_VAL 33
#define SPI_MAX_CLOCK_40_MHZ_VAL 40
#define SPI_MAX_CLOCK_50_MHZ_VAL 50
#define SPI_MAX_CLOCK_20_MHZ 0x00
#define SPI_MAX_CLOCK_25_MHZ 0x01
#define SPI_MAX_CLOCK_33_MHZ 0x02
#define SPI_MAX_CLOCK_40_MHZ 0x03
#define SPI_MAX_CLOCK_50_MHZ 0x04
#define SPI_MAX_CLOCK_20_MHZ 0x00
#define SPI_MAX_CLOCK_25_MHZ 0x01
#define SPI_MAX_CLOCK_33_MHZ 0x02
#define SPI_MAX_CLOCK_40_MHZ 0x03
#define SPI_MAX_CLOCK_50_MHZ 0x04
#define SPI_MAX_CLOCK_MASK 0xF8
#define SPI_CLOCK_RATIO_1_VAL 1
#define SPI_CLOCK_RATIO_2_VAL 2
#define SPI_NORMAL_MODE_VAL "normal"
#define SPI_SINGLE_MODE_VAL "fast"
#define SPI_DUAL_MODE_VAL "dual"
#define SPI_QUAD_MODE_VAL "quad"
#define SPI_CLOCK_RATIO_1 0x07
#define SPI_CLOCK_RATIO_2 0x08
#define SPI_NORMAL_MODE 0x00
#define SPI_SINGLE_MODE 0x01
#define SPI_DUAL_MODE 0x03
#define SPI_QUAD_MODE 0x04
#define SPI_NORMAL_MODE_VAL "normal"
#define SPI_SINGLE_MODE_VAL "fast"
#define SPI_DUAL_MODE_VAL "dual"
#define SPI_QUAD_MODE_VAL "quad"
#define FLASH_SIZE_1_MBYTES_VAL 1
#define FLASH_SIZE_2_MBYTES_VAL 2
#define FLASH_SIZE_4_MBYTES_VAL 4
#define FLASH_SIZE_8_MBYTES_VAL 8
#define FLASH_SIZE_16_MBYTES_VAL 16
#define SPI_NORMAL_MODE 0x00
#define SPI_SINGLE_MODE 0x01
#define SPI_DUAL_MODE 0x03
#define SPI_QUAD_MODE 0x04
#define FLASH_SIZE_1_MBYTES 0x01
#define FLASH_SIZE_2_MBYTES 0x03
#define FLASH_SIZE_4_MBYTES 0x07
#define FLASH_SIZE_8_MBYTES 0x0F
#define FLASH_SIZE_16_MBYTES 0x1F
#define SPI_UNLIMITED_BURST_ENABLE 0x08
#define FLASH_SIZE_1_MBYTES_VAL 1
#define FLASH_SIZE_2_MBYTES_VAL 2
#define FLASH_SIZE_4_MBYTES_VAL 4
#define FLASH_SIZE_8_MBYTES_VAL 8
#define FLASH_SIZE_16_MBYTES_VAL 16
#define FLASH_SIZE_1_MBYTES 0x01
#define FLASH_SIZE_2_MBYTES 0x03
#define FLASH_SIZE_4_MBYTES 0x07
#define FLASH_SIZE_8_MBYTES 0x0F
#define FLASH_SIZE_16_MBYTES 0x1F
/* Header fields default values. */
#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL
#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE
#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL
#define FW_CRC_START_ADDR 0x00000000
#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL
#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE
#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL
#define FW_CRC_START_ADDR 0x00000000
#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F
#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003
#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F
#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003
#define MAX_FLASH_SIZE 0x03ffffff
#define MAX_FLASH_SIZE 0x03ffffff
/* Chips: convert from name to index. */
#define NPCX5M5G 0
#define NPCX5M6G 1
#define NPCX5M5G 0
#define NPCX5M6G 1
#define NPCX7M5 2
#define NPCX7M6 3
#define NPCX7M7 4
#define NPCX5M5G_RAM_ADDR 0x100A8000
#define NPCX5M5G_RAM_SIZE 0x20000
#define NPCX5M6G_RAM_ADDR 0x10088000
#define NPCX5M6G_RAM_SIZE 0x40000
#define DEFAULT_CHIP NPCX5M5G
#define NPCX5M5G_RAM_ADDR 0x100A8000
#define NPCX5M5G_RAM_SIZE 0x20000
#define NPCX5M6G_RAM_ADDR 0x10088000
#define NPCX5M6G_RAM_SIZE 0x40000
#define NPCX7M5X_RAM_ADDR 0x100A8000
#define NPCX7M5X_RAM_SIZE 0x20000
#define NPCX7M6X_RAM_ADDR 0x10090000
#define NPCX7M6X_RAM_SIZE 0x40000
#define NPCX7M7X_RAM_ADDR 0x10070000
#define NPCX7M7X_RAM_SIZE 0x60000
/*---------------------------------------------------------------------------
Typedefs
@@ -171,6 +191,7 @@ struct tbinparams {
unsigned int anchor;
unsigned short ext_anchor;
unsigned char spi_max_clk;
unsigned char spi_clk_ratio;
unsigned char spi_read_mode;
unsigned char err_detec_cnf;
unsigned int fw_load_addr;
@@ -179,10 +200,10 @@ struct tbinparams {
unsigned int fw_err_detec_e_addr;
unsigned int fw_len;
unsigned int flash_size;
unsigned int hdr_crc;
unsigned int fw_crc;
unsigned int fw_hdr_offset;
unsigned int bin_params;
unsigned int hdr_crc;
unsigned int fw_crc;
unsigned int fw_hdr_offset;
unsigned int bin_params;
} bin_params_struct;
enum verbose_level {