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npcx: set and clear wake masks in S0 <-> S0ix transitions

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In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear
the wake masks when the SMI is invoked. For S0ix, EC sets and clears
the wake mask via this patch.

These functions are directly invoked from the state machine transition
states. During S0ix entry, the wake mask for lid open is enabled.
During S0ix exit, the wake mask for lid open is cleared. All pending
events are also cleared.

BRANCH=none
BUG=chrome-os-partner:58740
TEST=test lidopen in S0ix

Change-Id: I398fdba2b9bba1f6caef46f8dc71c7de3b669d08
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401070
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Archana Patni
2016-10-21 23:42:19 +05:30
committed by chrome-bot
parent 430dd5e644
commit edaedfaab4
1 changed files with 50 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
chip/npcx/lpc.c
View File

@@ -15,6 +15,7 @@
#include "host_command.h"
#include "keyboard_protocol.h"
#include "lpc.h"
#include "lpc_chip.h"
#include "port80.h"
#include "pwm.h"
#include "registers.h"
@@ -24,7 +25,6 @@
#include "uart.h"
#include "util.h"
#include "system_chip.h"
#include "lpc_chip.h"
/* Console output macros */
#if !(DEBUG_LPC)
@@ -1104,3 +1104,52 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
lpc_get_protocol_info,
EC_VER_MASK(0));
#ifdef CONFIG_POWER_S0IX
static void lpc_clear_host_events(void)
{
while (lpc_query_host_event_state() != 0)
;
}
/*
* In AP S0 -> S3 & S0ix transitions,
* the chipset_suspend is called.
*
* The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)
* is used to detect the S0ix transiton.
*
* During S0ix entry, the wake mask for lid open is enabled.
*/
void lpc_enable_wake_mask_for_lid_open(void)
{
if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) {
uint32_t mask;
mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) |
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN);
lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask);
}
}
/*
* In AP S0ix & S3 -> S0 transitions,
* the chipset_resume hook is called.
*
* During S0ix exit, the wake mask for lid open is disabled.
* All pending events are cleared
*/
void lpc_disable_wake_mask_for_lid_open(void)
{
if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) {
uint32_t mask;
mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) &
~EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN);
lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask);
lpc_clear_host_events();
}
}
#endif