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https://github.com/Telecominfraproject/OpenCellular.git
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it83xx: Complete EC interrupt list
There are more EC interrupts available. Also, update interrupts that should be reserved. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Use 'task_enable_irq()' to enable new-added interrupts and corresponding bit of interrupt enable register are set properly. Change-Id: If1aecec7e208782b4580e33efb968095f30794fe Reviewed-on: https://chromium-review.googlesource.com/344822 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Dino Li
@@ -22,13 +22,13 @@ static const struct {
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} irq_groups[21] = {
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IRQ_GROUP(0, {-1, 2, 5, 4, 6, 2, 2, 4}),
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IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8}),
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IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, -1}),
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IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12}),
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IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2}),
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IRQ_GROUP(4, {11, 11, 11, 11, 8, 9, 9, 9}),
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IRQ_GROUP(5, {-1, -1, -1, -1, -1, -1, -1, -1}),
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IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(7, {10, 10, 3, -1, 3, 3, 3, 3}),
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IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, 12, 12}),
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IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12}),
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IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2}),
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IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2}),
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@@ -37,10 +37,10 @@ static const struct {
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IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, -1}),
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IRQ_GROUP(17, {-1, -1, -1, -1, -1, -1, -1, -1}),
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IRQ_GROUP(18, { 2, 2, 2, 2, 2, 4, 4, 7}),
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IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(18, {-1, -1, -1, -1, -1, 4, 4, 7}),
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IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3}),
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IRQ_GROUP(20, {12, 12, -1, -1, -1, 12, 12, -1}),
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IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, 12}),
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};
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int chip_enable_irq(int irq)
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@@ -11,6 +11,7 @@
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#include "common.h"
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/* IRQ numbers */
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/* Group 0 */
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#define IT83XX_IRQ_WKO20 1
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#define IT83XX_IRQ_KBC_OUT 2
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#define IT83XX_IRQ_PMC_OUT 3
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@@ -18,6 +19,7 @@
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#define IT83XX_IRQ_WKINTAD 5
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#define IT83XX_IRQ_WKO23 6
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#define IT83XX_IRQ_PWM 7
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/* Group 1 */
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#define IT83XX_IRQ_ADC 8
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#define IT83XX_IRQ_SMB_A 9
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#define IT83XX_IRQ_SMB_B 10
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@@ -26,6 +28,7 @@
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#define IT83XX_IRQ_WKINTC 13
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#define IT83XX_IRQ_WKO25 14
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#define IT83XX_IRQ_CIR 15
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/* Group 2 */
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#define IT83XX_IRQ_SMB_C 16
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#define IT83XX_IRQ_WKO24 17
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#define IT83XX_IRQ_PS2_2 18
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@@ -33,6 +36,8 @@
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#define IT83XX_IRQ_PS2_0 20
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#define IT83XX_IRQ_WKO22 21
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#define IT83XX_IRQ_SMFI 22
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#define IT83XX_IRQ_USB 23
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/* Group 3 */
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#define IT83XX_IRQ_KBC_IN 24
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#define IT83XX_IRQ_PMC_IN 25
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#define IT83XX_IRQ_PMC2_OUT 26
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@@ -41,6 +46,7 @@
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#define IT83XX_IRQ_EGPC 29
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#define IT83XX_IRQ_EXT_TIMER1 30
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#define IT83XX_IRQ_WKO21 31
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/* Group 4 */
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#define IT83XX_IRQ_GPINT0 32
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#define IT83XX_IRQ_GPINT1 33
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#define IT83XX_IRQ_GPINT2 34
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@@ -49,6 +55,16 @@
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#define IT83XX_IRQ_SSPI 37
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#define IT83XX_IRQ_UART1 38
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#define IT83XX_IRQ_UART2 39
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/* Group 5 */
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#define IT83XX_IRQ_WKO50 40
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#define IT83XX_IRQ_WKO51 41
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#define IT83XX_IRQ_WKO52 42
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#define IT83XX_IRQ_WKO53 43
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#define IT83XX_IRQ_WKO54 44
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#define IT83XX_IRQ_WKO55 45
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#define IT83XX_IRQ_WKO56 46
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#define IT83XX_IRQ_WKO57 47
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/* Group 6 */
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#define IT83XX_IRQ_WKO60 48
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#define IT83XX_IRQ_WKO61 49
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#define IT83XX_IRQ_WKO62 50
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@@ -57,6 +73,7 @@
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#define IT83XX_IRQ_WKO65 53
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#define IT83XX_IRQ_WKO66 54
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#define IT83XX_IRQ_WKO67 55
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/* Group 7 */
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#define IT83XX_IRQ_RTCT_ALARM1 56
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#define IT83XX_IRQ_RTCT_ALARM2 57
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#define IT83XX_IRQ_EXT_TIMER2 58
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@@ -64,6 +81,7 @@
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#define IT83XX_IRQ_TMR_A1 61
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#define IT83XX_IRQ_TMR_B0 62
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#define IT83XX_IRQ_TMR_B1 63
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/* Group 8 */
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#define IT83XX_IRQ_PMC2EX_OUT 64
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#define IT83XX_IRQ_PMC2EX_IN 65
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#define IT83XX_IRQ_PMC3_OUT 66
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@@ -71,6 +89,7 @@
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#define IT83XX_IRQ_PMC4_OUT 68
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#define IT83XX_IRQ_PMC4_IN 69
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#define IT83XX_IRQ_I2BRAM 71
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/* Group 9 */
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#define IT83XX_IRQ_WKO70 72
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#define IT83XX_IRQ_WKO71 73
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#define IT83XX_IRQ_WKO72 74
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@@ -79,13 +98,16 @@
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#define IT83XX_IRQ_WKO75 77
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#define IT83XX_IRQ_WKO76 78
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#define IT83XX_IRQ_WKO77 79
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/* Group 10 */
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#define IT83XX_IRQ_EXT_TMR8 80
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#define IT83XX_IRQ_SMB_CLOCK_HELD 81
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#define IT83XX_IRQ_CEC 82
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#define IT83XX_IRQ_H2RAM_LPC 83
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#define IT83XX_IRQ_HW_KB_SCAN 84
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#define IT83XX_IRQ_WKO88 85
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#define IT83XX_IRQ_WKO89 86
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#define IT83XX_IRQ_WKO90 87
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/* Group 11 */
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#define IT83XX_IRQ_WKO80 88
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#define IT83XX_IRQ_WKO81 89
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#define IT83XX_IRQ_WKO82 90
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@@ -94,6 +116,7 @@
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#define IT83XX_IRQ_WKO85 93
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#define IT83XX_IRQ_WKO86 94
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#define IT83XX_IRQ_WKO87 95
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/* Group 12 */
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#define IT83XX_IRQ_WKO91 96
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#define IT83XX_IRQ_WKO92 97
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#define IT83XX_IRQ_WKO93 98
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@@ -102,6 +125,7 @@
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#define IT83XX_IRQ_WKO96 101
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#define IT83XX_IRQ_WKO97 102
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#define IT83XX_IRQ_WKO98 103
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/* Group 13 */
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#define IT83XX_IRQ_WKO99 104
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#define IT83XX_IRQ_WKO100 105
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#define IT83XX_IRQ_WKO101 106
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@@ -110,6 +134,7 @@
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#define IT83XX_IRQ_WKO104 109
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#define IT83XX_IRQ_WKO105 110
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#define IT83XX_IRQ_WKO106 111
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/* Group 14 */
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#define IT83XX_IRQ_WKO107 112
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#define IT83XX_IRQ_WKO108 113
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#define IT83XX_IRQ_WKO109 114
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@@ -118,6 +143,7 @@
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#define IT83XX_IRQ_WKO112 117
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#define IT83XX_IRQ_WKO113 118
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#define IT83XX_IRQ_WKO114 119
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/* Group 15 */
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#define IT83XX_IRQ_WKO115 120
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#define IT83XX_IRQ_WKO116 121
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#define IT83XX_IRQ_WKO117 122
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@@ -126,6 +152,7 @@
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#define IT83XX_IRQ_WKO120 125
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#define IT83XX_IRQ_WKO121 126
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#define IT83XX_IRQ_WKO122 127
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/* Group 16 */
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#define IT83XX_IRQ_WKO128 128
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#define IT83XX_IRQ_WKO129 129
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#define IT83XX_IRQ_WKO130 130
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@@ -133,9 +160,20 @@
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#define IT83XX_IRQ_WKO132 132
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#define IT83XX_IRQ_WKO133 133
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#define IT83XX_IRQ_WKO134 134
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/* Group 17 */
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#define IT83XX_IRQ_WKO136 136
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#define IT83XX_IRQ_WKO137 137
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#define IT83XX_IRQ_WKO138 138
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#define IT83XX_IRQ_WKO139 139
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#define IT83XX_IRQ_WKO140 140
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#define IT83XX_IRQ_WKO141 141
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#define IT83XX_IRQ_WKO142 142
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#define IT83XX_IRQ_WKO143 143
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/* Group 18 */
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#define IT83XX_IRQ_PMC5_OUT 149
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#define IT83XX_IRQ_PMC5_IN 150
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#define IT83XX_IRQ_V_COMP 151
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/* Group 19 */
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#define IT83XX_IRQ_SMB_E 152
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#define IT83XX_IRQ_SMB_F 153
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#define IT83XX_IRQ_OSC_DMA 154
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@@ -144,14 +182,16 @@
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#define IT83XX_IRQ_EXT_TIMER5 157
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#define IT83XX_IRQ_EXT_TIMER6 158
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#define IT83XX_IRQ_EXT_TIMER7 159
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/* Group 20 */
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#define IT83XX_IRQ_PECI 160
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#define IT83XX_IRQ_SOFTWARE 161
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#define IT83XX_IRQ_WKO162 162
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#define IT83XX_IRQ_WKO163 163
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#define IT83XX_IRQ_WKO164 164
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#define IT83XX_IRQ_ESPI 162
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#define IT83XX_IRQ_ESPI_VW 163
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#define IT83XX_IRQ_PCH_P80 164
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#define IT83XX_IRQ_USBPD0 165
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#define IT83XX_IRQ_USBPD1 166
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#define IT83XX_IRQ_WKO167 167
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#define IT83XX_IRQ_ESPI_SLAVE 167
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#define IT83XX_IRQ_COUNT 168
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/* IRQ dispatching to CPU INT vectors */
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@@ -177,6 +217,7 @@
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#define IT83XX_CPU_INT_IRQ_20 8
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#define IT83XX_CPU_INT_IRQ_21 2
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#define IT83XX_CPU_INT_IRQ_22 12
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#define IT83XX_CPU_INT_IRQ_23 12
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#define IT83XX_CPU_INT_IRQ_24 5
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#define IT83XX_CPU_INT_IRQ_25 4
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#define IT83XX_CPU_INT_IRQ_26 4
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@@ -193,6 +234,14 @@
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#define IT83XX_CPU_INT_IRQ_37 9
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#define IT83XX_CPU_INT_IRQ_38 9
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#define IT83XX_CPU_INT_IRQ_39 9
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#define IT83XX_CPU_INT_IRQ_40 2
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#define IT83XX_CPU_INT_IRQ_41 2
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#define IT83XX_CPU_INT_IRQ_42 2
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#define IT83XX_CPU_INT_IRQ_43 2
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#define IT83XX_CPU_INT_IRQ_44 2
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#define IT83XX_CPU_INT_IRQ_45 2
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#define IT83XX_CPU_INT_IRQ_46 2
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#define IT83XX_CPU_INT_IRQ_47 2
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#define IT83XX_CPU_INT_IRQ_48 2
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#define IT83XX_CPU_INT_IRQ_49 2
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#define IT83XX_CPU_INT_IRQ_50 2
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@@ -214,7 +263,6 @@
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#define IT83XX_CPU_INT_IRQ_67 4
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#define IT83XX_CPU_INT_IRQ_68 4
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#define IT83XX_CPU_INT_IRQ_69 4
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#define IT83XX_CPU_INT_IRQ_70 12
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#define IT83XX_CPU_INT_IRQ_71 12
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#define IT83XX_CPU_INT_IRQ_72 2
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#define IT83XX_CPU_INT_IRQ_73 2
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@@ -279,11 +327,14 @@
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#define IT83XX_CPU_INT_IRQ_132 2
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#define IT83XX_CPU_INT_IRQ_133 2
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#define IT83XX_CPU_INT_IRQ_134 2
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#define IT83XX_CPU_INT_IRQ_144 2
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#define IT83XX_CPU_INT_IRQ_145 2
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#define IT83XX_CPU_INT_IRQ_146 2
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#define IT83XX_CPU_INT_IRQ_147 2
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#define IT83XX_CPU_INT_IRQ_148 2
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#define IT83XX_CPU_INT_IRQ_136 2
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#define IT83XX_CPU_INT_IRQ_137 2
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#define IT83XX_CPU_INT_IRQ_138 2
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#define IT83XX_CPU_INT_IRQ_139 2
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#define IT83XX_CPU_INT_IRQ_140 2
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#define IT83XX_CPU_INT_IRQ_141 2
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#define IT83XX_CPU_INT_IRQ_142 2
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#define IT83XX_CPU_INT_IRQ_143 2
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#define IT83XX_CPU_INT_IRQ_149 4
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#define IT83XX_CPU_INT_IRQ_150 4
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#define IT83XX_CPU_INT_IRQ_151 7
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