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cr50: introduce means of detecting chip running in factory mode
When installed in the factory test rig, the DIOB4 pin is set to high by the moment the RW section starts. Software behavior needs to change to comply with the factory test rig requirements. Define the GPIO and add a function to report the factory mode state. BRANCH=cr50 BUG=b:63686091 TEST=tested along with the rest of the stack of patches. Change-Id: I8c4158fc75138d717fc009496365c8e61b42a890 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579584 Reviewed-by: Nick Sanders <nsanders@chromium.org>
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chrome-bot
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@@ -1641,3 +1641,17 @@ static int command_board_properties(int argc, char **argv)
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}
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DECLARE_SAFE_CONSOLE_COMMAND(brdprop, command_board_properties,
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NULL, "Display board properties");
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int chip_factory_mode(void)
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{
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static uint8_t mode_set;
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/*
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* Bit 0x2 used to indicate that mode has been set, bit 0x1 is the
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* actual indicator of the chip factory mode.
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*/
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if (!mode_set)
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mode_set = 2 | !!gpio_get_level(GPIO_DIOB4);
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return mode_set & 1;
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}
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@@ -222,6 +222,9 @@ void board_reboot_ap(void);
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int board_wipe_tpm(void);
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int board_is_first_factory_boot(void);
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/* Returns True if chip is brought up in a factory test harness. */
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int chip_factory_mode(void);
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#endif /* !__ASSEMBLER__ */
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/* USB interface indexes (use define rather than enum to expand them) */
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@@ -91,6 +91,9 @@ GPIO(SPI_MOSI, PIN(0, 7), GPIO_INPUT)
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GPIO(SPI_CLK, PIN(0, 8), GPIO_INPUT)
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GPIO(SPI_CS_L, PIN(0, 9), GPIO_INPUT)
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/* Used during *chip* factory process. */
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GPIO(DIOB4, PIN(0, 10), GPIO_INPUT | GPIO_PULL_DOWN)
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/* GPIOs used for Cr50 strapping options */
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GPIO(STRAP_A0, PIN(1, 12), GPIO_INPUT)
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GPIO(STRAP_A1, PIN(1, 13), GPIO_INPUT)
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@@ -190,4 +193,8 @@ PINMUX(GPIO(DETECT_SERVO), B5, DIO_INPUT)
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PINMUX(GPIO(SPI_MOSI), A4, DIO_OUTPUT)
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PINMUX(GPIO(SPI_CLK), A8, DIO_OUTPUT)
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PINMUX(GPIO(SPI_CS_L), A14, DIO_OUTPUT)
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PINMUX(GPIO(DIOB4), B4, DIO_INPUT)
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#undef PINMUX
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