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pyro/snappy: Enter/exit from S0ix based on host commands from kernel

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Follow reef setting.

This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.

The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
        ________                        ________
SLP_S0          |______________________|
        _____                             ________
HC           |___________________________|

BUG=none
BRANCH=reef
TEST=make buildall

Change-Id: I1073b5cb2cbb8492cec0967f2a6004c5ce368ecb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426558
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Bruce
2017-01-10 13:42:28 +08:00
committed by chrome-bot
parent 0ad4297190
commit ef85513be4
6 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/pyro/board.c
View File

@@ -117,7 +117,6 @@ void tablet_mode_interrupt(enum gpio_signal signal)
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L"},
{GPIO_PCH_SLP_S0_L, 1, "PMU_SLP_S0_N"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
{GPIO_SUSPWRNACK, 1, "SUSPWRNACK_DEASSERTED"},

3
board/pyro/board.h
View File

@@ -116,6 +116,8 @@
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_S0IX
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
/* EC */
#define CONFIG_ADC
@@ -228,7 +230,6 @@ enum pwm_channel {
enum power_signal {
X86_RSMRST_N = 0,
X86_SLP_S0_N,
X86_SLP_S3_N,
X86_SLP_S4_N,
X86_SUSPWRDNACK,

2
board/pyro/gpio.inc
View File

@@ -21,7 +21,6 @@ GPIO_INT(USB_C0_CABLE_DET, PIN(C, 5), GPIO_INT_RISING, anx74xx_cable_det_interru
GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */
GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */
GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
GPIO_INT(SUSPWRNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(RSMRST_L_PGOOD, PIN(6, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */
GPIO_INT(ALL_SYS_PGOOD, PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */
@@ -65,6 +64,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT)
GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */
GPIO(PCH_SCI_L, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SCI_ODL */
GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT) /* SLP_S0_L */
/*
* BRD_ID1 is a an ADC pin which will be used to measure multiple values.

1
board/snappy/board.c
View File

@@ -117,7 +117,6 @@ void tablet_mode_interrupt(enum gpio_signal signal)
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L"},
{GPIO_PCH_SLP_S0_L, 1, "PMU_SLP_S0_N"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
{GPIO_SUSPWRNACK, 1, "SUSPWRNACK_DEASSERTED"},

3
board/snappy/board.h
View File

@@ -115,6 +115,8 @@
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_S0IX
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
/* EC */
#define CONFIG_ADC
@@ -226,7 +228,6 @@ enum pwm_channel {
enum power_signal {
X86_RSMRST_N = 0,
X86_SLP_S0_N,
X86_SLP_S3_N,
X86_SLP_S4_N,
X86_SUSPWRDNACK,

2
board/snappy/gpio.inc
View File

@@ -21,7 +21,6 @@ GPIO_INT(USB_C0_CABLE_DET, PIN(C, 5), GPIO_INT_RISING, anx74xx_cable_det_interru
GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */
GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */
GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
GPIO_INT(SUSPWRNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(RSMRST_L_PGOOD, PIN(6, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */
GPIO_INT(ALL_SYS_PGOOD, PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */
@@ -65,6 +64,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT)
GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */
GPIO(PCH_SCI_L, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SCI_ODL */
GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT) /* SLP_S0_L */
/*
* BRD_ID1 is a an ADC pin which will be used to measure multiple values.