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stm32f0: Fix EC slave I2C interrupt
The interrupt handler is hardcoded to I2C1. We should choose between I2C1 and I2C2 based on I2C_PORT_EC. BUG=chrome-os-partner:30707 TEST=On Ryu, ectool hello and see ACK. BRANCH=None Change-Id: I07055b0ee7459e6cac5585737e200ff2d5814a34 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209960 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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chrome-internal-fetch
parent
f307874380
commit
f4ebbb821b
@@ -32,6 +32,14 @@
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*/
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#define I2C_MAX_HOST_PACKET_SIZE 128
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#ifdef HAS_TASK_HOSTCMD
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#if (I2C_PORT_EC == STM32_I2C1_PORT)
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#define IRQ_SLAVE STM32_IRQ_I2C1
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#else
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#define IRQ_SLAVE STM32_IRQ_I2C2
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#endif
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#endif
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/**
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* Wait for ISR register to contain the specified mask.
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*
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@@ -261,7 +269,7 @@ static void i2c_event_handler(int port)
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}
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}
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void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
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DECLARE_IRQ(STM32_IRQ_I2C1, i2c2_event_interrupt, 2);
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DECLARE_IRQ(IRQ_SLAVE, i2c2_event_interrupt, 2);
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#endif
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/*****************************************************************************/
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@@ -424,7 +432,7 @@ static void i2c_init(void)
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STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
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| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE;
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STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 | CONFIG_HOSTCMD_I2C_SLAVE_ADDR;
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task_enable_irq(STM32_IRQ_I2C1);
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task_enable_irq(IRQ_SLAVE);
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#endif
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}
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DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_DEFAULT);
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