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gma: Program PCH_RAWCLK_FREQ register

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This seems to be a scratchpad register to tell later drivers which
frequency the platform uses. Linux reads this but never writes the
register.

Change-Id: I55af7c7b675da580c7f52d9997262b232019132c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17071
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
2016-10-20 14:17:18 +02:00
committed by Nico Huber
parent 125a29e842
commit f54d096201
4 changed files with 32 additions and 3 deletions
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14
common/hw-gfx-gma-config.ads.template
View File

@@ -203,4 +203,18 @@ is
when Sandybridge => Full_Training,
when others => Auto_Training);
----------------------------------------------------------------------------
Default_RawClk_Freq : constant Frequency_Type :=
(case CPU is
when Ironlake |
Sandybridge |
Ivybridge => 125_000_000,
when Haswell |
Broadwell => (if CPU_Var = Normal then
125_000_000
else
24_000_000),
when Skylake => 24_000_000);
end HW.GFX.GMA.Config;

4
common/hw-gfx-gma-registers.ads
View File

@@ -349,7 +349,7 @@ is
PCH_FPB0,
PCH_FPB1,
PCH_DREF_CONTROL,
RAWCLK_FREQ,
PCH_RAWCLK_FREQ,
PCH_DPLL_SEL,
PCH_PP_STATUS,
PCH_PP_CONTROL,
@@ -1014,7 +1014,7 @@ is
TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
RAWCLK_FREQ => 16#0c_6204# / Register_Width,
PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
QUIRK_C2004 => 16#0c_2004# / Register_Width);
subtype Registers_Index is Registers_Invalid_Index range

15
common/hw-gfx-gma.adb
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@@ -78,6 +78,16 @@ is
----------------------------------------------------------------------------
PCH_RAWCLK_FREQ_MASK : constant := 16#3ff# * 2 ** 0;
function PCH_RAWCLK_FREQ (Freq : Frequency_Type) return Word32
is
begin
return Word32 (Freq / 1_000_000);
end PCH_RAWCLK_FREQ;
----------------------------------------------------------------------------
function To_GPU_Port
(Configs : Configs_Type;
Idx : Config_Index)
@@ -712,6 +722,11 @@ is
-------------------- Now restart from a clean state ---------------------
Power_And_Clocks.Initialize;
Registers.Unset_And_Set_Mask
(Register => Registers.PCH_RAWCLK_FREQ,
Mask_Unset => PCH_RAWCLK_FREQ_MASK,
Mask_Set => PCH_RAWCLK_FREQ (Config.Default_RawClk_Freq));
Initialized := True;
end Initialize;

2
common/hw-gfx.ads
View File

@@ -42,7 +42,7 @@ package HW.GFX is
Stride => 1,
Offset => 0);
subtype Frequency_Type is Pos64 range 25_000_000 .. 600_000_000;
subtype Frequency_Type is Pos64 range 24_000_000 .. 600_000_000;
type DP_Lane_Count is (DP_Lane_Count_1, DP_Lane_Count_2, DP_Lane_Count_4);
subtype DP_Lane_Count_Type is Pos64 range 1 .. 4;