chip: it83xx: Optimize interrupt usage of LPC access

LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.

Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

board/it83xx_evb/board.h

@@ -17,11 +17,11 @@
 #define CONFIG_FANS 1
 #define CONFIG_I2C
 #define CONFIG_I2C_MASTER
-#define CONFIG_IT83XX_LPC_ACCESS_INT
 #define CONFIG_IT83XX_SMCLK2_ON_GPC7
 #define CONFIG_KEYBOARD_BOARD_CONFIG
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LOW_POWER_S0
 #define CONFIG_PECI_TJMAX 100
 #define CONFIG_POWER_BUTTON
 /* Use CS0 of SSPI */

chip/it83xx/clock.c

@@ -96,8 +96,8 @@ void clock_init(void)
 
 	clock_module_disable();
 
-#if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT)
-	IT83XX_WUC_WUESR4 = 0xff;
+#ifdef CONFIG_LPC
+	IT83XX_WUC_WUESR4 = (1 << 2);
 	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
 	/* bit2, wake-up enable for LPC access */
 	IT83XX_WUC_WUENR4 |= (1 << 2);
@@ -229,6 +229,12 @@ void clock_sleep_mode_wakeup_isr(void)
 		clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff);
 		task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
 		process_timers(0);
+#ifdef CONFIG_LPC
+		/* disable lpc access wui */
+		task_disable_irq(IT83XX_IRQ_WKINTAD);
+		IT83XX_WUC_WUESR4 = (1 << 2);
+		task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
+#endif
 		/* disable uart wui */
 		uart_exit_dsleep();
 		/* Record time spent in sleep. */
@@ -258,14 +264,15 @@ void __idle(void)
 		if (DEEP_SLEEP_ALLOWED)
 			allow_sleep = clock_allow_low_power_idle();
 
-#if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT)
-		task_enable_irq(IT83XX_IRQ_WKINTAD);
-#endif
 		if (allow_sleep) {
 			interrupt_disable();
 			/* reset low power mode hw timer */
 			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1);
 			sleep_mode_t0 = get_time();
+#ifdef CONFIG_LPC
+			/* enable lpc access wui */
+			task_enable_irq(IT83XX_IRQ_WKINTAD);
+#endif
 			/* enable uart wui */
 			uart_enter_dsleep();
 			/* enable hw timer for deep doze / sleep mode wake-up */
@@ -283,9 +290,6 @@ void __idle(void)
 			asm("standby wake_grant");
 			idle_doze_cnt++;
 		}
-#if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT)
-			task_disable_irq(IT83XX_IRQ_WKINTAD);
-#endif
 	}
 }
 #endif /* CONFIG_LOW_POWER_IDLE */

chip/it83xx/gpio.c

@@ -481,11 +481,10 @@ static void __gpio_irq(void)
 	}
 #endif
 
-	if (irq == IT83XX_IRQ_WKINTAD) {
-		IT83XX_WUC_WUESR4 = 0xff;
-		task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
+#ifdef CONFIG_LPC
+	if (irq == IT83XX_IRQ_WKINTAD)
 		return;
-	}
+#endif
 
 	/*
 	 * Clear the WUC status register. Note the external pin first goes

core/nds32/task.c

@@ -76,11 +76,6 @@ void __idle(void)
 	cprints(CC_TASK, "idle task started");
 
 	while (1) {
-#if defined(CHIP_FAMILY_IT83XX) && defined(CONFIG_LPC) \
-	&& defined(CONFIG_IT83XX_LPC_ACCESS_INT)
-		task_enable_irq(IT83XX_IRQ_WKINTAD);
-#endif
-
 #ifdef CHIP_FAMILY_IT83XX
 		/* doze mode */
 		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
@@ -91,11 +86,6 @@ void __idle(void)
 		 * (sleep / deep sleep, depending on chip config).
 		 */
 		asm("standby wake_grant");
-
-#if defined(CHIP_FAMILY_IT83XX) && defined(CONFIG_LPC) \
-	&& defined(CONFIG_IT83XX_LPC_ACCESS_INT)
-		task_disable_irq(IT83XX_IRQ_WKINTAD);
-#endif
 	}
 }
 #endif /* !CONFIG_LOW_POWER_IDLE */

include/config.h

@@ -1183,9 +1183,6 @@
  */
 #undef CONFIG_IT83XX_ILM_BLOCK_SIZE
 
-/* LPC cycle can wake-up EC from doze / deep doze mode if define it. */
-#undef CONFIG_IT83XX_LPC_ACCESS_INT
-
 /* To define it, if I2C channel C and PECI used at the same time. */
 #undef CONFIG_IT83XX_SMCLK2_ON_GPC7