npcx: flash: Add write-protect support for internal flash of npcx7 ec

In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.

This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
   write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.

BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
     Build poppy board and upload FW to platform. No issues found.
     Passed flash write-protect checking on npcx796f evb.

Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>

chip/npcx/flash.c

@@ -191,6 +191,18 @@ static uint8_t flash_get_status2(void)
 	return ret;
 }
 
+#ifdef NPCX_INT_FLASH_SUPPORT
+static void flash_protect_int_flash(int enable)
+{
+	/*
+	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
+	 * only rebooting EC can clear it.
+	 */
+	if (enable && !IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF))
+		SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
+}
+#endif
+
 #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
 
 void flash_get_mfr_dev_id(uint8_t *dest)
@@ -263,6 +275,14 @@ static int flash_set_status_for_prot(int reg1, int reg2)
 		flash_uma_lock(0);
 	}
 
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now before setting them.
+	 */
+#ifdef NPCX_INT_FLASH_SUPPORT
+	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
+#endif
+
 	/* Lock physical flash operations */
 	flash_lock_mapped_storage(1);
 
@@ -308,6 +328,14 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
 	uint8_t sr1, sr2;
 	int rv = EC_SUCCESS;
 
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now.
+	 */
+#ifdef NPCX_INT_FLASH_SUPPORT
+	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
+#endif
+
 	sr1 = flash_get_status1();
 	sr2 = flash_get_status2();
 
@@ -647,6 +675,14 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 
 int flash_pre_init(void)
 {
+	/*
+	 * Protect status registers of internal spi-flash if WP# is active
+	 * during ec initialization.
+	 */
+#ifdef NPCX_INT_FLASH_SUPPORT
+	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
+#endif
+
 	/* Enable FIU interface */
 	flash_pinmux(1);
 

chip/npcx/gpio.c

@@ -360,6 +360,14 @@ void gpio_pre_init(void)
 	int flags;
 	int i, j;
 
+#ifdef CHIP_FAMILY_NPCX7
+	/*
+	 * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
+	 * for more information. It will be fixed in next chip.
+	 */
+	SET_BIT(NPCX_DEVCNT, 7);
+#endif
+
 	/* Pin_Mux for FIU/SPI (set to GPIO) */
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);

common/spi_flash_reg.c

@@ -63,6 +63,16 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */
 	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */
 };
+
+#elif defined(CONFIG_SPI_FLASH_W25Q80)
+static const struct protect_range spi_flash_protect_ranges[] = {
+	/* CMP = 0 */
+	{ 0, X, X, { 0, 0, 0 }, 0, 0 },       /* No protection */
+	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */
+	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */
+	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */
+};
+
 #endif
 
 /**