Chip level I2C transfer called from common was huge and
consumed 96 bytes of stack. Refactor into subfunctions
for master transmit and receive. Update I2C configuration
to program proper register values for bus clock and other
registers. Port switching modified to only switch ports
if necessary. Make port switch more robust by resetting
I2C controller clearing hardware state machines. Read
raw SCL and SDA signals using GPIO API instead of I2C
bit-bang register. I2C bit-bang only useful if I2C is
idle.
BRANCH=None
BUG=None
TEST=Configure board for port switching and I2C stress
tests.
CQ-DEPEND=CL:1053576
Change-Id: I647ecec8746dc9741c59879db15d7ad4e20e0469
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053880
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Hibernation timer was not programmed to correct value for
some cases and code was duplicated. Not all interrupt sources
were properly configured in system hibernate. Remove debug
only system pre-init board level call.
BRANCH=none
BUG=none
TEST=Build all boards using chip mchp. Test with EC UART
hibernate command.
CQ-DEPEND=CL:1053576
Change-Id: I932443fa7a4e284168babdbb7f64033a55427fb2
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053956
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Prevent WDT from firing while JTAG is attached without
having to completely remove watchdog feature. When new
chip debug feature is enabled attached a JTAG cable pulling
JTAG TRST# pin high will prevent watchdog timer from counting
down. Replacing the JTAG cable with a weak pull down will
allow WDT to operate normally.
BRANCH=None
BUG=None
TEST=Build all boards using chip mchp.
Change-Id: I54c52bd1ba2115491e63882c91a6ab4827918784
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053950
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For npcx ec, board driver needs to add GPIO_SEL_1P8V flag for SDA/SCL
pins in gpio.inc when i2c port is configured to support low-voltage
mode (1.8V). Npcx gpio driver will set the corresponding bits in
LV_GPIO_CTL register later. But if there is an i2c unwedging mechanism
occurred on those 1.8V i2c port, the bits of LV_GPIO_CTL will be cleared
unexpectedly after unweding is completed. And it also will make ec
consumes more 0.5mA current on each pin since IO is selected to 3.3V.
The root cause is the GPIO flags of SCL/SDA have been changed to
zero only after i2c unweding is done. This CL which solved this issue
includes:
1. Add GPIO_INPUT and GPIO_SEL_1P8V flag in ALTERNATE macro array which
pins belong to 1.8V i2c port.
2. Change type of flags in structure gpio_alt_func from uint16_t to
uint32_t since bit overflow.
BRANCH=none
BUG=b:109884927
TEST=No build errors for npcx7 series. Saving 3.3mW power consumption on
yorp if this patch is applied.
Change-Id: I06eadd5df36c7f69e6741f1dee13c801bac18360
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1089604
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The SPDX_LICENSE_TAG doesn't apply to the ec codebase since it would
want us to add the SPDX-License-Identifier to every file.
BRANCH=none
BUG=none
TEST=verified a new file does not need SPDX-License-Identifier tag
Change-Id: Ie7670f52ecd7a5dd825a56a0e8dc839e66ddd6f1
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1098026
Reviewed-by: Mike Frysinger <vapier@chromium.org>
With the Cortex-M7 core on STM32H7, the imprecise bus abort triggered by
the flash permission check might be propagated rather than ignored as we
might have gone through the ignore_bus_fault(0) before the exception
actually happens.
We need barriers to avoid this case, add one in flash_physical_protect_now
where I missed it in my previous patch.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75068419
TEST=On ZerbleBarn with MPU on and caches enabled, verify that
flash_physical_protect_now() no longer triggers an imprecise abort in
some builds.
Change-Id: I1b5159e6606336a196b93cb1210cc28acd47c5a4
Reviewed-on: https://chromium-review.googlesource.com/1096765
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Rule 5.7: A tag name shall be a unique identifier
Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7
Fixed For:
make ARM_TSP_RAM_LOCATION=tdram LOG_LEVEL=50 PLAT=fvp SPD=opteed
Change-Id: I5fbb5d6ebddf169550eddb07ed880f5c8076bb76
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7
To prevent violation of directive 4.5 having variable name channel
in css_pm_scmi.c not being typographically ambiguous change macro
argument CHANNEL in css_mhu_doorbell.h change argument to _channel
to fit with our convention which is a permitted exception of
directive 4.5 for this project
Rule 5.7: A tag name shall be a unique identifier
Fixed for:
make LOG_LEVEL=50 PLAT=juno
Change-Id: I147cdb13553e83ed7df19149b282706db115d612
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Rule 5.7: A tag name shall be a unique identifier
There were 2 amu_ctx struct type definitions:
- In lib/extensions/amu/aarch64/amu.c
- In lib/cpus/aarch64/cpuamu.c
Renamed the latter to cpuamu_ctx to avoid this name clash
To avoid violation of Rule 8.3 also change name of function
amu_ctxs to unique name (cpuamu_ctxs) since it now returns a
different type (cpuamu_ctx) than the other amu_ctxs function
Fixed for:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=juno
Change-Id: I575fbc96e8267f2b075e88def1f6e3185394613a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make PLAT=fvp USE_COHERENT_MEM=0
Change-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make PLAT=fvp SPD=tspd
Change-Id: I2d711b9584c4cb9ba3814ecd2ca65a42b7e24179
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Conflict with function name and variable name within that function.
Change the name of the function from image_size to get_image_size
to remove conflict and make the function fit the normal project
naming convention.
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: I1a63d2730113e2741fffa79730459c584b0224d7
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Rule 5.1: External identifiers shall be distinct
Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.
Fixed for:
LOG_LEVEL=50 PLAT=fvp
Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Instead of checking each directory in series, kick off all the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder from 31 seconds to 6.
Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge
branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the
newly created directory `scripts`. Here is the original commit message
from 2009.
> commit 8e54701ea85b0ab0971637825a628f5aa2b678a4
> Author: Andi Kleen <andi@firstfloor.org>
> Date: Sat Jan 3 03:21:41 2009 +0100
>
> kconfig: add script to manipulate .config files on the command line
>
> I often change single options in .config files. Instead of using
> an editor or one of the frontends it's convenient to do this from
> the command line. It's also useful to do from automated build scripts
> when building different variants from a base config file.
>
> I extracted most of the CONFIG manipulation code from one of my
> build scripts into a new shell script scripts/config
>
> The script is not integrated with the normal Kconfig machinery
> and doesn't do any checking against Kconfig files, but just manipulates
> that text format. This is always done at make time anyways.
>
> I believe this script would be a useful standard addition for scripts/*
>
> Sample usage:
>
> ./scripts/config --disable smp
> Disable SMP in .config file
>
> ./scripts/config --file otherdir/.config --module e1000e
> Enable E1000E as module in otherdir/.config
>
> ./scripts/config --state smp
> y
> Check state of config option CONFIG_SMP
>
> After merging into git please make scripts/config executable
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Change-Id: Ie32a4459398df8694956dd644f38692017a26388
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26243
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
on the npcx7, GPIOC2 is a bit special because it has 2 alternate
modes. we want the PWM1 mode instead of I2C6, and that's selected
using a special #define.
BUG=b:94613023,b:78309559
BRANCH=none
TEST=apshutdown still works
Change-Id: Ibd8baa15640344ce6c48b2c849e0d9fe6ce4239f
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1090320
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
set the input level for the PROCHOT# signal to 1.8v. the signal is
actually pulled up to 1.0v on the board so it has always read as
0 with the default 3.3v GPIO setting
now, with the 1.8v pin configuration, it actually reads as a 1:
> gpioget ec_prochot_odl
1 EC_PROCHOT_ODL
>
BUG=b:109846359
BRANCH=none
TEST=read back gpio pin state from EC console
Change-Id: Ibd25fdb10b15e42a03e460a43c118d1bc8971281
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1090319
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The FACTORY_DISABLE vendor command could return VENDOR_RC_INTERNAL_ERROR
in which case the EC error code is included in the response payload.
Print both errors if rv is nonzero and the response size is 1.
BUG=none
BRANCH=none
TEST=run 'gsctool -a -F disable' and make sure the vc and ec errors are
printed correctly.
Change-Id: Idc75d6d809865f1f3b685ca775ffbef9f6a1d860
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1096103
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The slave ports of LD20 CCI-500 are connected as follows:
S0: CA53
S1: CA72
Be careful because the slave interface is not arranged in the
cluster number order (CA72: cluster 0, CA53: cluster 1).
Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com>
Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
P256 key provisioning is complete, let's move RMA unlock to p256, this
frees up 5328 bytes in the flash.
BRANCH=cr50, cr50-mp
BUG=b:73296606
TEST=verified that dev key is properly accepted by the server, prod
key will be tested when prod image is signed.
Change-Id: I7d86bb2b793c32181f47f5354ad9db603aa49881
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1095535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The alternate mode for i2c still needs to set the 1.8V flag since it is
called when configuring the port initially and when it finishes
manually unwedging the port.
BRANCH=none
BUG=b:109884927
TEST=builds
Change-Id: Iafa87d3420a3605c0ad87bf8e1f5d69c3edb167a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096020
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The alternate mode for i2c still needs to set the 1.8V flag since it is
called when configuring the port initially and when it finishes
manually unwedging the port.
BRANCH=none
BUG=b:109884927
TEST=builds
Change-Id: Iac34c413499dfa803b45ec575f0a134774951b6c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096019
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Widen the flags field from 16-bit to 32-bit to fit all of the
current GPIO_flags. Also reorder fields within struct to allow arm
compiler to use 16-bit instructions instead of 32-bit instructions when
accessing fields (which is important for kevin board, otherwise
it runs out of space)
Lastly, re-tool macros to all reordering of gpio_alt_func struct fields.
BRANCH=none
BUG=b:109884927
TEST=builds on all boards
Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096018
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On TI platforms the UART is disabled by default and must be explicitly
enabled using the MDR1 register.
NOTE: The original definition of
http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but
many TI SoCs implementing 16550 do have a quirky MDR register
implemented. So, this should be enabled with TI_16550_MDR_QUIRK
NOTE: In such implementation, the CSR register does not exist.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
For the BL2_AT_EL3 configuration, move BL2 higher up to make more
space for BL31. Adjust the BL31 limit to be up to BL2 base. This is
because BL2 is always resident for the BL2_AT_EL3 configuration and
thus we cannot overlay it with BL31.
Change-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Rule 21.15: The pointer arguments to the Standard Library functions
memcpy, memmove and memcmp shall be pointers to qualified or unqualified
versions of compatible types.
Basically that means that both pointer arguments must be of the same
type. However, even if the pointers passed as arguments to the above
functions are of the same type, Coverity still thinks it's a violation
if we do pointer arithmetics directly at the function call. Thus the
pointer arithmetic operations were moved outside of the function
argument.
First detected on the following configuration
make PLAT=fvp LOG_LEVEL=50
Change-Id: I8b912ec1bfa6f2d60857cb1bd453981fd7001b94
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
