The signer script is checking the elf files for presence of test RMA
keys, currently hardcoded to be x25519 keys.
The algorithm (x25519 vs p256) is going to become a compile time
option, the script should be prepared to determine the type of the key
at run time, because the script could be used for signing images from
different branches, compiled with different config options.
The prod p256 key does not yet exist.
BRANCH=none
BUG=b:73296606
TEST=verified that prod signing images including x25519 keys is still
working as expected.
Change-Id: Icf48845279912ecc9ccdecec1764fcb5f85d22bd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1079698
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
- Change GPIO signals at runtime based on board version
- SYS_RESTET_L, ENTERING_RW, USB2_OTG_ID
- Add 2nd signal for 2nd USB-A port BC1.2 outbound charging
- (GPIO96) USB_A1_CHARGE_EN_L (V1) maps to EN_BRD_ID (V0) so we
can just enable the USBA port 1 signal on V0 with only a small
power drain. It is not worth the EC codebase churn to add support
for changing the number of USB-A ports at runtime (since it is a compile
time constant now)
- Yorp V0 is the only board that set USB_PORT_COUNT to 1 so we can make
common octopus code only have the 2 port case.
- Add placeholders for LED_3_L, WFCAM_VSYNC
- Updated signal name comments to match schematics
- Formatting cleanup for consistency
BRANCH=none
BUG=b:109747036,b:74388692
TEST=verified `sysjump rw` does not brown out board when only powering
with USB C1 without battery. Since GPIO_C1_EN_SNK_V0 moved, the board would
lock power out if GPIOs state was not maintained properly through
sysjump transition.
Change-Id: Ie4c72699ab23ee6f7d2fa77a78709e5b4343e46f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1087815
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
During compilation sconfig/main.c gives an error regarding number of
arguments passed in fprintf.
BUG=none
BRANCH=none
TEST=check if compilation warning has been fixed
Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change gets rid of unused 3rd parameter chips to the function
walk_device_tree.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: I255ff030562073b16310fc22a0981808bf2c062f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update to current master.
This includes:
- G45 support
- fixes scaling on eDP (needed for working textmode on eDP)
- gfx_test drawing and moving cursors
- Adding support for Tiling on <= Haswell
- Allow changes to the framebuffer configurarion without resetting the
pipe.
Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26823
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When debugging HW write protect you can use the AP to tell what the
actual HW write protect setting is, but you can't tell what cr50 thinks
the HW write protect setting is. This change adds cr50 support for
getting the HW write protect using a vendor command.
This adds 98 bytes
BUG=b:77543904
BRANCH=cr50
TEST=none
Change-Id: I7410ecca557ad1fcf78e521623c4444b452fbc42
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1060641
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Hardware does not support ADCs for Vbus anymore for
all boards except bip. Make bip the same as other octopus
boards (i.e. not using ADCs for Vbus measurements).
BRANCH=none
BUG=b:109747036
TEST=CL stack works with current yorp
Change-Id: I96b82b70799e8b70bf5d479a1714524fc1652140
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1089199
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Full panel initialization can take about 1.6 seconds. If this is
called by hook_call_deferred, it will block other HOOKS. Replace the
'while loop + sleep' by re-calling deferred every 100ms.
BRANCH=whiskers
BUG=b:109714732
TEST=sudo ./extra/usb_updater/usb_updater2 -d 18d1:5030 --tp_update <fw>
TEST=sudo extra/usb_updater/usb_updater2 -d 18d1:5030 --tp_debug=01
TEST=(EC console) touchpad_st calibrate
Signed-off-by: Wei-Han Chen <stimim@chromium.org>
Change-Id: I665169524a06a7c359303a4a3dceced4a141f9ae
Reviewed-on: https://chromium-review.googlesource.com/1086895
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Scan-build refuses to run if the -fconserve-stack flag is added to
cflags. It fails with the cryptic message "could not find clang line".
Change-Id: Ib1b56ef7d217138a1a195fe993d8e8dd965bd855
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
sn5s330_init() will turn off the PP1 (source) FET, but
sn5s330_is_sourcing_vbus() can be called before PPC init: by
usb_charger_init() and pd_power_supply_reset() from pd_task().
Keep track of the PP1 (source) FET state locally, and use this for
sn5s330_is_sourcing_vbus(), instead of reading the state from the PPC chip
over I2C every time.
This solves the problem of sn5s330_is_sourcing_vbus() being called before
sn5s330_init(), and also avoids other problems caused by
sn5s330_is_sourcing_vbus() doing I2C communication:
crrev.com/c/969701/7/board/cheza/board.c#85
BUG=b:80203727
BRANCH=none
TEST=Reboot Grunt EC while one USB-C port is VBUS source.
Change-Id: Ie0fdd3d672bc747fcdbb746586149e194165fdac
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1086115
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
usb_charger_init() did not call charge_manager_update_charge() if we are
sourcing VBUS. This means we can get stuck with charge_manager_is_seeded()
never returning true, and so charging never starts, and power-on is
prevented.
Change update_vbus_supplier() so it always calls
charge_manager_update_charge(), but with current = 0 when we are sourcing
VBUS.
BUG=b:80203727
BRANCH=none
TEST=Reboot Grunt EC while one USB-C port is VBUS source.
Change-Id: I24c29dc6b9ad9c50254181614a6440d2d055cd5a
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1086113
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch bumps up the BL1-RW size for Juno and at the same time reduces
the BL2 size when TBB is enabled, TF_MBEDTLS_KEY_ALG=rsa+ecdsa. The BL2
size for this config is reduced as it was observed that the peak memory
usage is only reached when SPD=opteed and the dual rsa+ecdsa support is
not needed for this case.
Change-Id: Ia9009771b5cfd805e9cc75410aabb7db99fc2fbc
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
When SMCCC_ARCH_WORKAROUND_1 is invoked from a lower EL running in
AArch32 state, ensure that the SMC call will take a shortcut in EL3.
This minimizes the time it takes to apply the mitigation in EL3.
When lower ELs run in AArch32, it is preferred that they execute the
`BPIALL` instruction to invalidate the BTB. However, on some cores
the `BPIALL` instruction may be a no-op and thus would benefit from
making the SMCCC_ARCH_WORKAROUND_1 call go through the fast path.
Change-Id: Ia38abd92efe2c4b4a8efa7b70f260e43c5bda8a5
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This patch updates the firmware design guide for the BL memory
layout change on ARM platforms.
Change-Id: Icbfe7249484bb8b4ba3c94421172d42f27605c52
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.
This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
* When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
* When BL2_AT_EL3=1 for BL2
The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.
Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
