This will be used as part of the checks for when to allow CCD open.
Add check for firmware space dev mode bit, based on the similar code
which reads the FWMP. Print the state of both bits in 'ccd get'.
BUG=b:79983505
BRANCH=cr50
TEST=With dev mode off, 'ccd get' does not report TPM: dev_mode.
Turn on dev mode via the recovery screen, and it does.
Change-Id: I6af78bb104004323cd377ed996e1db94bc36fc62
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1066391
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Observed VBOOT hash failure for EC_RW. Function
spi_flash_read with size > SPI_FLASH_MAX_READ_LEN
is incorrectly incrementing the offset. For example:
0, 0x100, 0x300, 0x600, all with read size = 256.
BUG=
BRANCH=any EC using SPI flash
TEST=Trigger VBOOT hash re-calculation using EC
console hash rw command. Second test program
SPI flash with known test pattern longer than
SPI_FLASH_MAX_READ_LEN and read using EC
console flashread.
Change-Id: I5fda47f132f64b12044b94663a19d889f1c2b32a
Reviewed-on: https://chromium-review.googlesource.com/1036258
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch ensures that user can select a specific AP to run
a function.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With CONFIG_BATTERY_REVIVE_DISCONNECT once the battery FULL flag gets
set, charge_state_v2 will call battery_get_disconnect_state. That
function had console print that's only meaningful when the battery is
actually disconnected. To avoid flooding the EC console log under this
expected condition, this CL moves the console log so that it only
happens when the battery is present, but disconnected.
BRANCH=none
BUG=b:79133101
TEST=Verfied that with full battery the console log message is no
longer showing. Also verifed that can recover from battery cutoff
condition.
Change-Id: Id2e161cbd52c0ef07f28b94608f9615071327c97
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1064975
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
compare_timestamp_entries will fail for entries that are different by
at least 2^32 since entry_stamp is 64-bit and the return for compare
is 32-bit. This change fixes compare_timestamps by actually comparing
the entries to return 1, -1 or 0 instead of doing math on them.
TEST=Verified that "cbmem -t" sorts entries correctly on previously
failing entries.
Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the recent change 4c518e1 (timestamp: Add timestamps for TPM
communication) to add more timestamps for TPM communication, now we
are overflowing the TIMESTAMP region in verstage. This change
increases TIMESTAMP region size to 512 bytes to accomodate this.
BUG=b:79888151, b:79974682
Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
As I mention in the comment, this is valid ASL, which was added as
a warning with the comment "This would appear to be worthless in
real-world ASL code." While code using empty resource templates
could probably be rewritten, this seems like an arbitrary choice
to generate this as a warning, since it's valid.
This gets rid of warnings such as this one:
dsdt.aml 2975: Return (ResourceTemplate() {})
Warning 3150 - Empty Resource Template (END_TAG only)
Which is generated by this code in google/rambi/acpi/mainboard.asl:
Method (_CRS)
{
/* Only return interrupt if I2C1 is PCI mode */
If (LEqual (\S1EN, 0)) {
Return (^RBUF)
}
/* Return empty resource template otherwise */
Return (ResourceTemplate() {})
}
Change-Id: I9cfe9069c738a284aa85feada9d58e1aee97e433
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26352
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ecst has two open-coded implementations of a function to inject a string
into another string (that happens to be a path). Factor out and make
sure that gcc 8.1's static analysis of string lengths is happy.
BUG=b:65441143
BRANCH=none
TEST=builds with gcc 8.1
Change-Id: I80581d26b6f75cac2c9530c18f94d12614aa1586
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1061878
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
gcc 8.1 complains about duplicate const, and while some of these really
are duplicate, others look like they were supposed to tighten the API
contract so that variables are "const pointer to const data", but didn't
have that effect.
BUG=b:65441143
BRANCH=none
TEST=building Chrome EC as part of upstream coreboot's build with a
gcc 8.1 compiler now works (better. there are other issues left)
Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1039812
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
GCC 8.1's linker tries to rewrite the code to match the lowest common
denominator, reintroducing references to __aeabi_idivmod and friends
even on ARM revisions that don't need them.
Tell it what it's linking for to keep it harmless.
BUG=b:65441143
BRANCH=none
TEST=make buildall works with gcc 8.1
Change-Id: I7296aa80f587aa4f004fb20958714766793ab2b5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1061693
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
there are no pullup resistors on the TCPC ALERT# pins and none on the
board, so we need to turn on internal pullups on the EC side.
BUG=b:75070158
BRANCH=none
TEST=board still boots
Change-Id: I15a7940d8b647b83c6ae304171c4a7c46b920529
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1059870
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Describe the USB devices in the devicetree so they can get
generated into the SSDT and presented to the OS.
This was tested on an eve board and the resulting SSDT was
verified to show the expected values in _UPC and _PLD.
Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb. This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default. The _PLD can also be customized for more accurate
descriptions if necessary.
This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB 2.0 Type-A""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
end
end
end
It will generate the following ACPI code in the SSDT:
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB 2.0 Type-A")
Name (_UPC, Package (0x04)
{
0xFF,
0x00,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "RECTANGLE",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
)
}
Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.
Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
In case the Option ROM isn't a multiple of 4KiB the last buffer was
truncated to prevent a buffer overrun. But tests on nouveau showed
that nouveau expects a buffer that has the requested size and is zero
padded instead.
Always return a buffer with requested size and zero pad the remaining
bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple
of 4 KiB.
Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
The `-t` argument was never required for `add-payload` and results in
a warning now because the type was renamed.
TEST=Built with BUILD_TIMELESS=1 and compared binaries with and without
this patch.
Change-Id: I6ccb70acc6e88a602b90c625040d4f05d8e3630a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26323
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements support for adding dynamic configurations for
BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The
necessary cert tool support and changes to default chain of trust are made
for these configs.
Change-Id: I25f266277b5b5501a196d2f2f79639d838794518
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This patch adds capability to FVP to disable authentication dynamically
via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses
the TB_FW_CONFIG for the `disable_auth` property and invokes the
`load_dyn_disable_auth()` API to disable authentication if the
property is set to 1. The DYN_DISABLE_AUTH is enabled by default for
FVP as it is a development platform. Note that the TB_FW_CONFIG has to
be authenticated by BL1 irrespective of these settings.
The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup()
rather than in bl2_platform_setup() as we need to get the value of
`disable_auth` property prior to authentication of any image by BL2.
Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This patch allows platforms to dynamically disable authentication of
images during cold boot. This capability is controlled via the
DYN_DISABLE_AUTH build flag and is only meant for development
purposes.
Change-Id: Ia3df8f898824319bb76d5cc855b5ad6c3d227260
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
The CNVi wifi/bt module prevents entry into S5 by keeping internal
SoC clocks running. Therefore it's necessary to disable BT prior to
S5 entry.
BUG=b:79606769
TEST= Test if BT device works under following cases:
1. Power-on
2. Press powerbtn before OS entry
3. Power-on from S5 again
Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before:
*** 4560 bytes still available in flash ****
After:
*** 4696 bytes still available in flash ****
BRANCH=none
BUG=b:65253310
TEST=Update Cr50 with this image and verify the keys are the same.
Change-Id: I1c722ced185c41f732ce0ed5236db01401f21dfc
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1031058
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch makes led_get_brightness_range return amber=100, white=100
regardless of OEM ID or led_id. This function is for ectool led command,
which is used to test basic LED connectivity.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:78489297,b:77827579
BRANCH=none
TEST=Run
1. ectool led battery white=100
2. ectool led battery amber=100
3. ectool led power white=100
4. ectool led power amber=100
Change-Id: I6c6b3a5dd26aaba3a3ff7dccd6e116794c6594c9
Reviewed-on: https://chromium-review.googlesource.com/1062077
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Gemini Lake-based chipsets support a subset of virtual wires that other
Intel processors do. The current settings prevent the GLK APs from
bootign in some situations; PLTRST# doesn't get reasserted when there is
an error.
See "eSPI Compatibility Specification (562633)" for details.
BRANCH=None
BUG=b:79778835
TEST=Successfully booted bip after a cold reset from servo
Change-Id: I02b403ab6b06cbcae61ac46132018e95988a3d43
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1064704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
They're only used within the same file and should always be inlined.
It also helps gcc 8.1's lto linking which seems to not inline it (since
inline is just a hint) but then drops the function (presumably because
it's small, marked inline, and comes with no prototype).
BUG=b:65441143
BRANCH=none
TEST=builds with gcc 8.1
Change-Id: I881a5b9f13192dd11748d8a3060788f95a84dec0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1061075
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This reverts commit cfcac78e62.
Reason for revert: Removing all s3 termination support. It's not
necessary and it causes scarlet to boot into recovery.
Original change's description:
> cr50: add support for enabling terminations on ap suspend
>
> rk3399 systems need terminations on the SPI signals in S3 and all other
> low power states. Add support for enabling the pulldowns and pullups on
> the correct pins.
>
> With this change, if BOARD_NEEDS_S3_TERM is set in the board properties,
> cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown
> on all of the SPS signals. To keep the pulldowns from interfering with
> the sps peripheral, s3_term will also disable the input for those
> signals.
>
> BUG=b:62200096
> BRANCH=cr50
> TEST=Flash onto bob. Make sure cr50 enables and disables terminations
> when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do
> anything.
>
> Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883
> Signed-off-by: Mary Ruthven <mruthven@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/991338
> Commit-Ready: Mary Ruthven <mruthven@chromium.org>
> Tested-by: Mary Ruthven <mruthven@chromium.org>
> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Bug: b:62200096
Change-Id: I00c5051a48d4578badf9ce6622dea1af9903f4fd
Reviewed-on: https://chromium-review.googlesource.com/1062687
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This reverts commit c24d480d90.
Reason for revert: Removing all s3 termination support. It's not
necessary and it causes scarlet to boot into recovery.
Original change's description:
> cr50: disable s3_terms during init
>
> When cr50 resumes from deep sleep term_enabled is reset to 0, but not
> all of the s3 termination settings are reset. Some of them are, because
> some of the gpios are defined in gpio.inc and cr50 will handle setting
> those up during init, but others like the sps pulldowns aren't. At this
> point, the term_enabled setting does not actually match the state of
> enabled terminations.
>
> After deep sleep reset if the AP is on, ccd update state will try to
> disable the s3 terminations, but term_enabled is 0, so s3_term thinks
> they're already disabled and wont do anything even though some of the
> terminations are actually enabled.
>
> This change initializes all of the s3_term stuff to disable during hook
> init. This way things are reset so they won't interfere with sps_init.
> This will also make sure to align the system state with term_enabled,
> before the ccd hook starts getting called. It is safer to start with
> disabling the terminations, because it wont interfere with tpm
> communication if the AP is on. If the AP is off, ccd_update_state will
> re-enable the terminations around a second after init.
>
> BUG=b:62200096,b:79214702
> BRANCH=cr50
> TEST=firwmare_Cr50DeepSleepStress.reboot on bob
>
> Change-Id: I9a90c7f7703b1406b4c494db448a8ac84d040d1c
> Signed-off-by: Mary Ruthven <mruthven@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/1043152
> Commit-Ready: Mary Ruthven <mruthven@chromium.org>
> Tested-by: Mary Ruthven <mruthven@chromium.org>
> Reviewed-by: Randall Spangler <rspangler@chromium.org>
> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Bug: b:62200096, b:79214702
Change-Id: If3467352030c65365c6851cd692aa5d0e9f47667
Reviewed-on: https://chromium-review.googlesource.com/1062686
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In 'console_set_scope' and when registering a console, field 'flags' of
'console_t' is assigned a 32-bit value. However, when it is actually
used, the functions perform 64-bit reads to access its value. This patch
changes all 64-bit reads to 32-bit reads.
Change-Id: I181349371409e60065335f078857946fa3c32dc1
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
