Using variables as format strings can generate security problems when
the user can control those strings. Some compilers generate warnings
in that cases, even when the variables are constants and are not
controlled by the user.
Change-Id: I65dee1d1b66feab38cbf298290a86fa56e6cca40
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Vendor code has several headers included into source code that are not
needed in order to build them. Remove unneeded #include. This is part of
controlling the build of unneeded procedures within vendor code.
BUG=b:78610011
TEST=Build grunt.
Change-Id: Id7d451b6be564632836fc64fd343131edb85183a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Newer versions of util-linux/mount don't like when you create overlapping
loopback files. Since we always create a loopback of the entire image,
this means every mount fails.
We can change the few users in here over to using the existing loopback
partitions rather than continuing to create their own from scratch. This
makes the code a bit simpler.
However, we currently duplicate some of the mount image helpers so that
one version works off of a disk image while the other uses loopbacks.
Cleaning this up requires a number of changes in other files which we'll
want to do eventually, just not right now (to minimize risk).
BUG=chromium:714598
TEST=image signing works on newer gLinux installs
BRANCH=None
Change-Id: I31b35636b3b271e97070d283f8cb74d3183d8ec8
Reviewed-on: https://chromium-review.googlesource.com/1034435
Commit-Ready: Mike Frysinger <vapier@chromium.org>
Tested-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Jason Clinton <jclinton@chromium.org>
In npcx5 series, there is no other chip generation and npcx's system
driver fixed the first character of revision array as 'A'. But in npcx7
series, there are two chip generations and it's better to show chip
generation information by 'version' console command.
In this CL, we used SRID_CR to distinguish the generation of npcx7
series. It also adds the support for NPCX787G in system_get_chip_name()
since it is used on the version 1 of npcx7 evb.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Verified npcx5m5g, npcx7m6g and
npcx7m7wb on evbs by 'version' console command.
Change-Id: I7572b5688b4430c6febd21c25f36c3903fb97e27
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1046689
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The ACOK_OD is a required signal of the charging state machine. EC
can't always hold it low; however, it breaks the charging state.
Make it back to EC input. There are some side-efforts, mentioned in
the bug.
BRANCH=none
BUG=b:78035750
TEST=Plugged/unplugged AC when AP is on/off.
TEST=Verified the power sequence still works.
Change-Id: I039af9cdb86cfb509f2580e6f57d82309825dac1
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1042620
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.
BUG=b:74617340
Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When we support the lowest power mode for Nuvoton in the next spin, we
will shed the TCPC/PPC power rail during hibernate. Before we drop the
power for the PPCs we need to ensure that Vbus is lower than the
hard-coded 6.8V dead-battery mode over-voltage threshold, otherwise we
will lock ourselves out of power.
BRANCH=none
BUG=b:79218851
TEST=verified that yorp renegotiates Vbus to 5V when entering hibernate
via ec `hibernate` cmd.
Change-Id: I4a98573eefb5757eea02dc48c64d5f9358b5e0b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047954
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Keep the timestamp of the latest power lost. Add a handler to wake
the chipset task to check if power lost stays low for a while (the
time between now and the latest power lost is longer than a period).
BRANCH=none
BUG=b:78455067
TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset
sequence and verified AP reset but not a transition S0 -> S5.
TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse
(see power_off function) to execute PMIC shutdown sequence and verified
a power-lost transition S0 -> S5.
Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028831
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising
edge interrupts to trigger a hook to call chipset_reset().
As the hook task will be preempted by the chipset task, it adds a
flag bypass_power_lost_trigger to avoid triggering to S5 as the
chipset state machines sees power lost during the reset.
So far the chipset_reset() implementation is to do a cold reset;
will be revised to a warm reset after the PMIC registers are
reprogrammed.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Ran 'reboot' on AP console which toggles the GPIO.
Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1023986
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On newer boards, FP_RST_ODL is no longer Open-Drain and has a 100k
pull-down. Drive it as push-pull.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:79277207
TEST=On ZerbleBarn, verify that the sensor comes up, has the right HWID
and can capture images.
TEST=On new boards, do the same.
Change-Id: I45e1ba41a7649e0682e3ea11dd0159f666286bba
Reviewed-on: https://chromium-review.googlesource.com/1049545
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The current PCH UART support for console is limited to UART2.
This change adds support for specifying UART0 or UART1 to be
used instead by changing CONFIG_UART_FOR_CONSOLE in the board
level Kconfig. The default is still 2.
This is tested with a board that uses UART0 for debug output.
Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/26140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
we need to configure EC_PROCHOT_ODL as an input because the EC isn't
driving it correctly. we changed the polarity of EC_PROCHOT for atlas
and similar boards, but the EC codebase has this hard-coded as
active-high.
this is a short-term fix until we implement a more general PROCHOT
"polarity" feature.
BUG=b:78911901,b:79266467
BRANCH=none
TEST=checked voltage drop across in-line resistor on EC_PROCHOT and
AP can now run above 400MHz
Change-Id: I8c3224c62ea7af4f386062d39c248d418e73fa53
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045556
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
the isl9238 needs to see a higher PPVAR_SYS voltage than we were using
to avoid tripping Low_VSYS. Low_VSYS is one of the terms causing the
isl9238 to assert PROCHOT. its lowest default voltage threshold is
about 6.1v which is too close to the battery "minimum" that we were
using to set PPVAR_SYS. it's better to use the "normal" battery
voltage so the running-on-AC case is similar to the running-on-battery
case.
BUG=b:78911901
BRANCH=none
TEST=examined isl9238 regs to verify it is no longer tripping Low_VSYS
Change-Id: Iafc39e988a5af668c6cc1b5485841f6d659b1e8b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1043456
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
