Commit Graph

41347 Commits

Author SHA1 Message Date
Raul E Rangel
d4fec689fd cbmem: Sort timestamp entries
If the timestamp entries are added out of order, the duration
calculation will be wrong.

AGESA collects timestamp data through all the stages. Then in AmdInitPost
it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then
take the data and call timestamp_add on each entry. This results in
the entries being out of order.

TEST=Built firmware for grunt that manually added entries and then ran
cbmem -t/-T to verify the entries were in the correct order.

Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26168
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13 10:14:35 +00:00
Noah Glovsky
7f268eab78 mainboard/asus: Add license headers
Change-Id: I71e461b91f981368d4bd13631b868430d1fc5774
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13 10:13:32 +00:00
xiinc37
8a2b7f31fb mainboard/hp: Add HP Elitebook 8770w
This is based on the code from the 8470p port. Tested on the quad
core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics
cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The
laptop must be completely disassembled down to the motherboard to
perform the initial flash, subsequent flashes can be done internally
via flashrom. There is a simple mod that can be performed to make
subsequent external flashes easier in case of a brick, I'll put more
information on this on the wiki later. The lack of an MXM structure
built in to the firmware causes the GPU to enter a mode with nerfed
performance, there is a workaround though, I'll add this to the wiki
as well. I have no info on EHCI debugging.

Tested and working:
- memory: 4G+4G, 4G+4G+4G+4G
- Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload
with graphics init disabled in coreboot. I allowed SeaBIOS to load the
VBIOS from the MXM.
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- VGA
- DisplayPort
- Audio
- Both HDD SATA ports, ODD SATA, eSATA
- S3 with SeaBIOS 1.11, SERCON must be disabled
- Brightness and volume FN keys
- Mute and calculator hotkeys
- Status LEDs
- Bluetooth

Not working:
- GRUB2 as payload will freeze. Has something to do with at_keyboard
module. The built in keyboard requires this module to function though.
- Sleep FN key
- WiFi toggle and internet browser hotkeys
- S3 fails to resume (restarts) if the laptop is removed from AC power,
or gets unplugged and then plugged back in while suspended. Sleep
status LEDs remain normal during this process.

Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a
Signed-off-by: Robert Reeves <xiinc37@gmail.com>
Reviewed-on: https://review.coreboot.org/23651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13 10:12:50 +00:00
Raul E Rangel
4c518e18e3 timestamp: Add timestamps for TPM communication
On grunt these operations combined take a little over 37ms.

BUG=b:64549506
TEST=built on grunt
 511:starting TPM PCR extend                           301,268 (598)
 512:finished TPM PCR extend                           326,710 (25,442)
 513:starting locking TPM                              326,716 (6)
 514:finished locking TPM                              339,517 (12,801)

Change-Id: I05cfb3d0f8463f073e329a035484a340546649e1
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26218
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13 10:08:42 +00:00
Lubomir Rintel
38686f15dd msrtool: add support for printing string values
The VIA CPUs allow setting the CPUID vendor, which is best read as
a character string.

Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-13 10:07:23 +00:00
Lubomir Rintel
199a23cd8a mstrool: only use intel targets for actual intel CPUs
VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite
Pentium III.

Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13 10:07:12 +00:00
Kevin Cody-Little
f5f552afcd superio/ite/it8623e: initialize the PWM fan controller
Copies the common/env_ctrl support code from the it8728f driver.

Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload,
and booting userspace without a kexec call.

Prior to this change, an error was given during boot:

it87 it87.656: Detected broken BIOS defaults, disabling PWM interface

After this change, the message is gone, and PWM fan control works
through the /sys/class/hwmon interface.

Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26224
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12 20:32:27 +00:00
Nico Huber
e100fe4a59 Revert "3rdparty/blobs: Update submodule marker for Intel microcode updates"
This reverts commit 0ff9daac45.

It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.

Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-12 20:17:02 +00:00
Stefan Adolfsson
74b5a2ccb5 npcx: CEC: Send CEC message in mkbp event
Instead of fetching incoming CEC messages using a specific read
command, extend the standard mkbp event so the CEC message can
be delivered directly inside the event.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST="ectool cec read" still working with a kernel that has support
for the increased mkbp size.
CQ-DEPEND=CL:1046186,CL:1051085

Change-Id: Id9d944be86ba85084b979d1df9057f7f3e7a1fd0
Reviewed-on: https://chromium-review.googlesource.com/1051105
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-12 12:06:06 -07:00
Furquan Shaikh
c6141b9451 mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filename
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.

BUG=b:79396300

Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-12 08:13:38 +00:00
Nick Sanders
53f61a76b7 servo_updater: support old and new updater
Add support for usb_updater2 in servo_updater.
This allows update back and forth between servo-9040.B
releases and builds from master, although they have
different updater enpoint interfaces.

Also add '-n' no force reboot to usb_updater2 as force reboot
is incompatible with servo_updater's flow.

BRANCH=None
BUG=b:69016431
TEST=update servo v4

Change-Id: I18809590c2e7e1cfcf60c4c97e956dfc22d85856
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1056157
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-05-11 23:22:26 -07:00
Caveh Jalali
0b6da3c5d8 charge_state_v2: keep track of AC_PRESENT flag
the EC should not clear the AC_PRESENT flag in the ACPI flags when we
know that we're on a charger.  ACPI rules on the AP side do special
things when they see AC_PRESENT off, like forcing the EC to limit the
charge current to 512mA.

BUG=b:78509594
BRANCH=none
TEST=chargestate current no longer stuck at 512mA

Change-Id: I54ddea6d2661a9d6b1593431a5912a8a60db572d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1050917
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-05-11 23:22:15 -07:00
Daisuke Nojiri
344e8220b5 lm3509: Avoid setting brightness to 100% on power-up
This patch makes lm3509 avoid setting the LED brightness to 100% on
power-up. It removes brighness control from lm3509_power entirely.
The brightness is controlled by the OS.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

BUG=b:78360907
BRANCH=none
TEST=Verify keyboard backlight turn on off on Nami as expected. No
flashing on start-up or resume is observed.

Change-Id: Ife82c83501d57aeb540acb1cccb95597fd1d19a0
Reviewed-on: https://chromium-review.googlesource.com/1054408
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11 12:10:44 -07:00
Daisuke Nojiri
94b4c511a6 kblight: Add keyboard backlight control module
This patch promotes board/nami/keyboard_backlight.c to common
directory.
Board customization is done via board_kblight_init callback.
It currently supports two drivers: direct PWM control and lm3509.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

BUG=b:78360907,b:78141647
BRANCH=none
TEST=On Nami (for lm3509) and Sona (pwm), verify the followings:
1. Alt + brightness up/down works
2. After suspend-resume, brightness is restored
3. Lid close/open
4. After screen is off, keyboard backlight is turned off

Change-Id: I584c06e8702fe7b289999698f277311cfd3400bd
Reviewed-on: https://chromium-review.googlesource.com/1051027
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 12:10:44 -07:00
Daisuke Nojiri
f21a0681c7 Nami: Read CBI early and cache it
This patch adds a HOOK_INIT handler which reads CBI. This handler runs
as early as I2C controller is ready so that all subsequent code can refer
to cached CBI.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

BUG=none
BRANCH=none
TEST=Verify CBI is read reliably on Nami at boot.

Change-Id: I979947d6bd63ce0cdc1400ba561c543d9ed7b40e
Reviewed-on: https://chromium-review.googlesource.com/1054341
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11 12:10:43 -07:00
Youness Alaoui
d319b98279 purism/librem_bdw: Rename Broadwell baseboard from BDL to BDW
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so
I'm renaming librem_bdl into librem_bdw and changing the KConfig
options accordingly.

Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26237
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 18:23:48 +00:00
Aaron Durbin
44f80657fd drivers/intel/gma: honor vbt_size parameter to locate_vbt()
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.

BUG=b:79562868

Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 18:16:13 +00:00
Stefan Adolfsson
89b8653e70 npcx: CEC: Add unit suffixes
Add unit suffixes to all timing constants and variables so it is
clear that it is ticks, not usec we are dealing with.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=emerge chromeos-ec
CQ-DEPEND=CL:1030371

Change-Id: I02883108b6f844a7a2d8f0fcd75edaecbbb8e403
Reviewed-on: https://chromium-review.googlesource.com/1046186
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:36 -07:00
Stefan Adolfsson
6415c19415 CEC: Group ectool subcommands under "ectool cec"
Instead of e.g. "ectool cecwrite", use "ectool cec write" to
not clutter the command list.

BUG=b:76467407
BRANCH=none
TEST=Run "cec read/write/get/set" and make sure they still
work.
CQ-DEPEND=CL:1030218

Change-Id: Id515782f5a5ff0861fb95ab63c45dc8ab153f0bb
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1046185
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 09:30:36 -07:00
Stefan Adolfsson
64cf05b7e8 npcx: CEC: Respect the present initiator free-time
When sending multiple frames, the free-time is a bit
higher to make it easier for other senders to get
a chance to send.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=none
CQ-DEPEND=CL:1030370

Change-Id: I19e510ec0b6e987e0d8477fa5549e0b29ef594ee
Reviewed-on: https://chromium-review.googlesource.com/1030371
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:35 -07:00
Stefan Adolfsson
ad01d0518b npcx: CEC: Get/set logical address
Logical address selection is best done from the AP since
it depends on what kind of CEC device type we want to be.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Set address to different values and verify that it
only receives messages on that address (or broadcast)
CQ-DEPEND=CL:1030229

Change-Id: Ia5ef182b22f2345831caaa7f29cc9f009f932c99
Reviewed-on: https://chromium-review.googlesource.com/1030370
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:35 -07:00
Stefan Adolfsson
edac0b1924 npcx: CEC: Add software debouncing
If pulses shorter than the CEC specification allows are detected,
ignore the bus for a while. This avoids CPU stress if there is a
misbehaving device sending short pulses on the CEC bus.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=none
CQ-DEPEND=CL:1030228

Change-Id: I55819f9437a00799718e235c30f256508465bf4c
Reviewed-on: https://chromium-review.googlesource.com/1030229
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:34 -07:00
Stefan Adolfsson
394ede0e6e npcx: CEC: Improve pulse-width measurements
Take into account the time from the interrupt is triggered until
the timer is set when recharging the timer.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Using temprorary debug-prints.
CQ-DEPEND=CL:1030227

Change-Id: Ia36bd73ff5efcff719db7b7915212f30a8e555f3
Reviewed-on: https://chromium-review.googlesource.com/1030228
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:34 -07:00
Stefan Adolfsson
38d90756cb npcx: CEC: Event-handling for incoming messages
When an incoming message is complete, store it in a
internal circular buffer and notify the AP so the
message can be read out.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Write different type of messages from one EC to another EC
using ectool. Also use ectool on the second EC to verify that
they are received correctly.
CQ-DEPEND=CL:1030226

Change-Id: Ie4370b0c954befe81a055cd5dff7d7f13dbefbd0
Reviewed-on: https://chromium-review.googlesource.com/1030227
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:34 -07:00
Stefan Adolfsson
8ba061a449 npcx: CEC: Handle incoming CEC messages
Adds handling of incoming messages:
* Start-bit detection
* ACK incoming messages
* Broadcast handling
* Pulse-width validation
* EOM detection

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Tested in later CL when messages are plumbed all the
way back to the AP.
CQ-DEPEND=CL:1030225

Change-Id: I541072b8afa3d911b310628f09f0b665f11a0a15
Reviewed-on: https://chromium-review.googlesource.com/1030226
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:33 -07:00
Stefan Adolfsson
ea5d72e85b npcx: CEC: Add bus-contention handling
If low-impedance is detected during the time from free-time
until the end of the initiator address, the current send is
postponed until the bus is free again.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=none
CQ-DEPEND=CL:1030224

Change-Id: If4b9ed43306cf2e38770085603f7fa83a1f76ddc
Reviewed-on: https://chromium-review.googlesource.com/1030225
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:33 -07:00
Stefan Adolfsson
e317b78cd3 npcx: CEC: Handle enable/disable command
The Linux kernel has enable/disable hooks in the CEC
driver API. Make it possible to use those calls on
the EC CEC implementation.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Verify with logical analyzer that nothing happens on
the bus in disable mode and it still works in enable mode.
CQ-DEPEND=CL:1030223

Change-Id: Ib5255d76427f288862740cd2e3299ba47f39d998
Reviewed-on: https://chromium-review.googlesource.com/1030224
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:32 -07:00
Stefan Adolfsson
2d1d3d68b0 npcx: CEC: Notify AP of CEC send result
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=ectool cecwrite with and without sink. Reports
success if there is a sink, else it fails.
CQ-DEPEND=CL:1030222

Change-Id: I28f12fd8e226e1e261efaeeefe60f257c0afadf9
Reviewed-on: https://chromium-review.googlesource.com/1030223
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:32 -07:00
Stefan Adolfsson
1ddb719bd0 npcx: CEC: Add resend-logic to CEC driver
According to the CEC specification, a resend must be
attempted at least once and up to five times after NAK.
This fix does it five times.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Write CEC message without sink. Verify with logical
analyzer that it resends 5 times.
CQ-DEPEND=CL:1030221

Change-Id: Id296e12b6657b9e7ca0453a2deb06e8aaf17f839
Reviewed-on: https://chromium-review.googlesource.com/1030222
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:31 -07:00
Stefan Adolfsson
e89486c9b6 npcx: CEC: Write messages on the CEC bus
Add hooks that ectool or AP will use to send CEC messages.
Messages are sent by setting a timer and flipping
a GPIO in the timer interrupt. The timer is then
recharged in inside that interrupt depending on
where it is in the CEC state-machine.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Switched on and off a TV:
ectool cecwrite 0x40 0x04
ectool cecwrite 0x40 0x36
CQ-DEPEND=CL:1030220

Change-Id: Ia640d0d035bcee9be88863046e88402c7a63c19f
Reviewed-on: https://chromium-review.googlesource.com/1030221
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-05-11 09:30:31 -07:00
Stefan Adolfsson
802337c26d npcx: CEC: Add stub implementation of CEC
Add CEC stub implementation and enable it for Fizz. All
it does is print a message when the driver is initialized.

Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>

BUG=b:76467407
BRANCH=none
TEST=Check that "CEC initialized" is printed on the
console when the EC boots.
CQ-DEPEND=CL:1030219

Change-Id: I1cf674e664e091354e344e0c08a69bd09f415904
Reviewed-on: https://chromium-review.googlesource.com/1030220
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 09:30:31 -07:00
Chris Kay
d0223211e8 css: Do not map the non-secure RAM as secure
Change-Id: I7e73c0ab134da11c49f990b739245110c59eac2b
Signed-off-by: Chris Kay <chris.kay@arm.com>
2018-05-11 15:37:54 +01:00
Chris Kay
d7ecac73b5 css: Fix erroneous non-secure RAM base address/size for SGI-575
SGI-575's NSRAM is neither in the same place nor the same size as Juno's.

Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823
Signed-off-by: Chris Kay <chris.kay@arm.com>
2018-05-11 15:37:47 +01:00
Chris Kay
053b4f92cb plat/arm: Fix incorrect bounds check in ARM_CASSERT_MMAP
The bounds check in ARM_CASSERT_MMAP does not take into account the
array sentinel in plat_arm_mmap. This commit fixes this, and adds an
additional check to ensure the number of entries in the array is
within the bounds of PLAT_ARM_MMAP_ENTRIES.

Change-Id: Ie6df10c0aa0890d62826bc3224ad7b3e36fd53e2
Signed-off-by: Chris Kay <chris.kay@arm.com>
2018-05-11 14:55:20 +01:00
Chris Kay
3450fd6224 plat/arm: Fix incorrect number of reserved memory map entries
There are three calls to mmap_add_region() that always occur in
arm_setup_page_tables(), and two further calls based on whether coherent
memory is enabled, and whether SPM is enabled in BL31.

This commit adapts the ARM_BL_REGIONS definition to match the number of
calls made inside arm_setup_page_tables() so that the MAX_MMAP_REGIONS
is realigned with what is actually occurring.

Change-Id: I7adc05951abccf2cbd5c86280eb874911e6a1566
Signed-off-by: Chris Kay <chris.kay@arm.com>
2018-05-11 14:55:20 +01:00
ren kuo
f064c75ae2 mainboard/google/coral: Override VBT selection for epaulette
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.

Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms

BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
     Run on DUT and check panel sequence meets spec.

Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 13:01:38 +00:00
ren kuo
88c9d98b64 mb/google/reef/variants/: Add new memory ID
Add a new RAM ID of memrory PN:MT53E512M32D2NP

BUG=b:78491470
TEST= emerge-coral coreboot chromeos-bootimage.

Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>

Change-Id: I855702c2850887df74941e00da69322124557498
Reviewed-on: https://review.coreboot.org/26213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
2018-05-11 13:01:15 +00:00
Dimitris Papastamos
da9d1d59d4 Merge pull request #1372 from antonio-nino-diaz-arm/an/arm-multi-console
Arm platforms: Migrate to multi console driver
2018-05-11 12:04:52 +01:00
Antonio Nino Diaz
b726c16907 plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
Normally, BL33 needs to contain a boot loader like U-Boot or UEFI that
eventually gives control to the OS. However, in some cases, this boot
sequence may be too slow. For example, when doing tests in a
cycle-accurate emulator, the user may only be interested in the
interaction between the Trusted Firmware and the OS, not in the boot
process itself.

The new option ARM_LINUX_KERNEL_AS_BL33 allows BL33 to contain the Linux
kernel image by changing the value of registers x0-x3 to the values
expected by the kernel. This option requires the device tree blob (DTB)
to be present in memory. Its address must be specified in the newly
introduced ARM_PRELOADED_DTB_BASE build option. For now, it only supports
AArch64 kernels.

This option is only available when RESET_TO_BL31=1. For this reason
the BL33 binary must be preloaded in memory and PRELOADED_BL33_BASE must
be used.

For example, if the kernel is loaded at 0x80080000 and the DTB is loaded
at address 0x82000000, the firmware could be built like this:

    CROSS_COMPILE=aarch64-linux-gnu-  \
    make PLAT=fvp DEBUG=1             \
    RESET_TO_BL31=1                   \
    ARM_LINUX_KERNEL_AS_BL33=1        \
    PRELOADED_BL33_BASE=0x80080000    \
    ARM_PRELOADED_DTB_BASE=0x82000000 \
    all fip

Change-Id: If9dc847c65ae2d0c27b51f0fd44fc06b28497db9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-11 11:15:10 +01:00
Philip Chen
13ea63266c scarlet: Enable AP throttling for battery OCP
BUG=b:74321682
BRANCH=scarlet
TEST=manually test on scarlet together with CL:994188

Change-Id: I831ca9941248835f98a1c5ea69e751f3f7413ed7
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1043454
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 02:58:50 -07:00
Philip Chen
43db76c108 Revert "scarlet: Limit the maximal acceptable VBUS to 5.5V"
This reverts commit c4e728e6f991537b5e0f715c4f9e946b029d5bd8.

BUG=b:78792296
BRANCH=scarlet
TEST=none

Change-Id: I4dc73e85cc7883ef4b2ab83da4d671a7709d9fd3
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1054121
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
2018-05-11 02:58:49 -07:00
Fabien Parent
e4b718df7a charge_manager: fix possible out of bound read access
The port id given by the kernel is never checked and out-of-bound
read accesses can be made on available_charge. Fix it.

Change-Id: I06ed3d28c30db77d8256e9af808484a7cbdc901e
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-on: https://chromium-review.googlesource.com/1046592
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 02:58:46 -07:00
Fabien Parent
7034d8b711 charge_manager: add host cmd to get port count
The kernel is only able to know the number of USB PD port through
EC_CMD_USB_PD_PORTS, but the kernel needs also to be able to know
that there is a dedicated port. Add a host command that will
return the total number of charge port (USB PD + BJ).

BRANCH=None
BUG=chromium:841944
TEST=Called command from kernel driver and checked that the port count
was the expected value.

Change-Id: I6ccd8a2dee35bbe8bb66dfbe09d1cc09c54b73a0
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-on: https://chromium-review.googlesource.com/1046593
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2018-05-11 02:58:45 -07:00
Antonio Nino Diaz
2f18aa1fa3 plat/arm: Migrate AArch64 port to the multi console driver
The old API is deprecated and will eventually be removed.

Arm platforms now use the multi console driver for boot and runtime
consoles. However, the crash console uses the direct console API because
it doesn't need any memory access to work. This makes it more robust
during crashes.

The AArch32 port of the Trusted Firmware doesn't support this new API
yet, so it is only enabled in AArch64 builds. Because of this, the
common code must maintain compatibility with both systems. SP_MIN
doesn't have to be updated because it's only used in AArch32 builds.
The TSP is only used in AArch64, so it only needs to support the new
API without keeping support for the old one.

Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this
causes the UARTs to reset (except for the one used by the TSP). This
means that they must be unregistered when suspending and re-registered
when resuming. This wasn't a problem with the old driver because it just
restarted the UART, and there were no problems associated with
registering and unregistering consoles.

The size of BL31 has been increased in builds with SPM.

Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-11 10:46:58 +01:00
Antonio Nino Diaz
c2e05bb78c multi console: Assert that consoles aren't registered twice
In the multi console driver, allowing to register the same console more
than once may result in an infinte loop when putc is called.

If, for example, a boot message is trying to be printed, but the
consoles in the loop in the linked list are runtime consoles, putc will
iterate forever looking for a console that can print boot messages (or
a NULL pointer that will never come).

This loop in the linked list can occur after restoring the system from a
system suspend. The boot console is registered during the cold boot in
BL31, but the runtime console is registered even in the warm boot path.
Consoles are always added to the start of the linked list when they are
registered, so this it what should happen if they were actually
different structures:

   console_list -> NULL
   console_list -> BOOT -> NULL
   console_list -> RUNTIME -> BOOT -> NULL
   console_list -> RUNTIME -> RUNTIME -> BOOT -> NULL

In practice, the two runtime consoles are the same one, so they create
this loop:

   console_list -> RUNTIME -.    X -> BOOT -> NULL
                       ^    |
                       `----'

This patch adds an assertion to detect this problem. The assertion will
fail whenever the same structure tries to be registered while being on
the list.

In order to assert this, console_is_registered() has been implemented.
It returns 1 if the specified console is registered, 0 if not.

Change-Id: I922485e743775ca9bd1af9cbd491ddd360526a6d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-11 10:39:07 +01:00
Iru Cai
056cbbe3f5 asrock/b75pro3-m: Add superio ACPI declarations
Without it the PS/2 keyboard doesn't work after booting into the OS.

Change-Id: Idcb0ea0779fcd5dfd6e0fbf33a532ecf0caec420
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/26131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:14:19 +00:00
Youness Alaoui
0cf89bf20a purism/librem_bdl: Add support for Librem 15 v2
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:09:20 +00:00
Youness Alaoui
b799e0df3d purism/librem_bdl: Convert to variant setup
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.

Also update the URL in board_info to an archive.org link.

Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:08:18 +00:00
Elyes HAOUAS
96184e9f2d nb/intel/i945/bootblock.c: Correct comment
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:05:40 +00:00
Elyes HAOUAS
322fa32e5e nb/intel/i440bx: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I69c8b95ff1937c0b08147d9e26a3118c58129cf5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-11 09:02:55 +00:00