This patch adds i2c suite to run_ects.py. It also adds checks for
return values from i2c_read and i2c_write functions.
BUG=chromium:653183
BRANCH=none
TEST=Run run_ects.py and verify all test pass.
Change-Id: Ie3d6e1e6f131235e2b28f39e1546c9cb4c3b92f6
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/547024
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since the script is expected to upload results and probably send
alerts by e-mail, it's better to be written in Python so that we
can utilize chromite library. It will no longer run outside chroot
because of imports from chromite.lib.
BUG=chromium:735546
BRANCH=none
TEST=Run run_ects.py and verify all tests pass.
Change-Id: I6c79b061cdaef4d30305cf531f37b6734d18b7d9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/546579
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch updates the mutex test suite so that it can be run
within the current framework.
BUG=chromium:736155
BRANCH=none
TEST=run cts.py -m mutex
test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT
lock_unlock_test SUCCESS SUCCESS 1 1 PASS
Change-Id: I69ee0857a0c633d7c6c8909f8c6f58ca6fd272ce
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/544790
This patch updates the hook test suite so that it can be run
within the current framework.
BUG=chromium:736047
BRANCH=none
TEST=cts.py -m hook
test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT
test_init_hook SUCCESS SUCCESS 1 1 PASS
test_ticks SUCCESS SUCCESS 1 1 PASS
test_priority SUCCESS SUCCESS 1 1 PASS
test_deferred SUCCESS SUCCESS 1 1 PASS
Change-Id: I3e7f29da61e794b06b03241f3d7706c2db94b5be
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/545084
This script will run nightly in the lab and publish the results.
Publishing results will be implemented later.
BUG=chromium:735546
BRANCH=none
TEST=Run run_ects.sh inside & outside chroot and verify all tests pass.
Change-Id: I405ea601eff33f1a4328f2606c8bb4050ff8d253
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/543681
In CL:503475, SERVO_TYPE is initialized *after* toad cable detection.
This make flash_ec failed to update plankton EC.
This CL adjust the timing of SERVO_TYPE detection, so toad cable
detection can work properly.
BUG=b:35648297
BRANCH=plankton
TEST=utils/flash_ec --board=plankton
Change-Id: I08a11b99109454096949b3ff64ed1c4d5f9891df
Reviewed-on: https://chromium-review.googlesource.com/535381
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using servo v4 with the captive CCD cable to flash an STM32 requires bit
banging mode to be enabled. This commit adds that support.
BUG=b:35648297
BRANCH=gru
TEST=Add support for rowan and flash rowan with no issues.
Change-Id: I6317d4acdd569888e20a1e298de7c8b620e94bb1
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/503476
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Not every servo has support for the same controls. For example, servo
micro doesn't have the JTAG buf on flex elements. This commit cleans up
the assumptions made and defines some variables which indicate which
controls are supported on a particular servo type. The servo type is
obtained by the "servo_type" control from servod.
BUG=b:35648297
BRANCH=gru
TEST=With some other patches, try and flash rowan with a servo v4.
Change-Id: Ie10f4f73028a01a81638e9114b48c88941b8bf93
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/503475
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
The recent change of the code signer is not backwards compatible, a
new command line parameter must be added.
BRANCH=cr50
BUG=none
TEST=verified that
H1_DEVIDS='xxxx yyyyy' ./util/signer/bs
succeeds again.
Change-Id: I9a8e03c20aa4b7b689b1f5e4a1f786cf5857483f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/527317
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add touchpad related host commands:
1) EC_CMD_TP_SELF_TEST: run open short test.
2) EC_CMD_TP_FRAME_INFO: get number of frame and frame size.
3) EC_CMD_TP_FRAME_SNAPSHOT: make a snapshot of the frame.
4) EC_CMD_TP_FRAME_GET: get frame data.
BRANCH=none
BUG=b:62077098
TEST=`make BOARD=rose -j`
`ectool --name=cros_tp tpselftest` and
`ectool --name=cros_tp tpframeget` works
Change-Id: I43db82278e556b1e6f6301fe88233fe7c4a18a14
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/515282
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Add support for i2c boot protocol 1.1 and erase non-strech erase
command.
Add option to specify i2c slave address.
TEST=Read, Erase and Write SH on Ryu P4.
BUG=chrome-os-partner:36018
BRANCH=none
Change-Id: Ib0649323fd8879fef6e2dc5e62001c891afe128a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/250101
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
The upcoming "real" signer update will introduce a version which is
not backwards compatible with the existing one wrt the command line
flags: the command line flag '-b' will have to be present.
To keep the default "dummy" signer in sync let's make it accept and
ignore the '-b' command line flag.
BRANCH=none
BUG=none
TEST=verified that the updated signer and the dummy signer both work.
Change-Id: Ia8ab6d7ae01d249046f267608b5971a7a7c95e29
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517678
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Move the existing fingerprint host command in the driver and
add more of them to prepare the new fingerprint architecture.
The commands are mostly stubbed for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
CQ-DEPEND=*364728
BRANCH=none
BUG=b:35648259
TEST=make BOARD=eve_fp (with and without a private repository)
do a fingerprint image capture with 'fptest'.
Change-Id: Ie17a5fde2d6470c6272e8059bddc845cea07aff2
Reviewed-on: https://chromium-review.googlesource.com/491071
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Adds min_frequency and max_frequency to struct motion_sensor_t.
New attributes min_frequency and max_frequency are now returned in
ectool's MOTIONSENSE_CMD_INFO response.
Incremented ectool's MOTIONSENSE_CMD_INFO version to version 3.
Add constants for MIN_FREQUENCY and MAX_FREQUENCY to each sensor's
header file.
BRANCH=none
BUG=chromium:615059
TEST=build/boot and verify MOTIONSENSE_CMD_INFO response on kevin,
make buildall -j passes.
Change-Id: I66db9715c122ef6bb4665ad5d086a9ecc9c7c93a
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482703
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add the evaluation board driver of npcx7 series ec for testing. If you
received the evb which ec is 128-pins package, please notice it has
the following limitations.
a. No GPIOD7/E0 pins.
b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports.
c. No ADC7, ADC8 and ADC9 channels.
d. No JTAG port 1.
e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb.
This CL also includes:
1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg.
Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ.
2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl.
3. Add npcx7_evb support in flash_ec.
BRANCH=none
BUG=none
TEST=Passed all npcx7 drivers verification on the evb no matter which
ec's package is 128 or 144 pins package.
Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
hammer corresponds to poppy, and staff corresponds to soraka.
Current differences (hammer/staff):
- USB id (5022/502b)
- PWM frequency (10kHz/100Hz):
- On staff, driving PWM at 10kHz leads to an actual duty cycle
around 30-40%, with a PWM output at 1% (long rise/fall time).
100Hz looks better, we get ~1.45% duty with 1% PWM output.
BRANCH=none
BUG=b:38277869
TEST=Flash staff, boots fine.
TEST=pwm 0 1 shows quite dim backlight on staff.
Change-Id: I66ba2adf89fbee8578ee473afb28e3e242b4d111
Reviewed-on: https://chromium-review.googlesource.com/505855
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In a lab servo, flash_ec is executed without the board flag. In this
case, don't check the board flag for raiden and simply respect the
raiden flag.
BRANCH=none
BUG=b:38319398
TEST=Ran the flash_ec script in a lab servo.
Change-Id: Ib3757a4b7b550fd77facffdf2009cc3317591888
Reviewed-on: https://chromium-review.googlesource.com/506461
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, when we jump from RO to RW, we forget our USB PD state.
To recover from this, we send a SOFT_RESET (resetting the counters...),
then either the USB PD partner is happy about it and we can continue,
or it will issue a HARD_RESET to recover from our mismatched vision of
the current connection (e.g wrong role) resulting in a reset of VBUS.
The following use-case is still problematic:
if the system is not write-protected (ie it does USB PD negotiation in
RO EC) and we have no battery (or fully drained-one) as buffer, when we
are connected to a PD power supply, if it issues the HARD_RESET
mentioned above, we are going to brown-out.
It's happening with power-supplies supporting DR_SWAP, the RO EC will
negotiate a power-contract (as a sink), then try to reverse data role
(from UFP to DFP) to identify the power-supply. We end-up being
Sink/DFP, then when we sysjump to RW, we reset roles and send the
SOFT_RESET as Sink/DFP, the power-supply identifies the incorrect data
role and issues the HARD_RESET browning us out.
As a workaround, now we never ask for the DR_SWAP in RO firmware and
stays Sink/UFP.
This is not affecting regular write-protected machines (which are not
doing USB PD in RO EC). For developers, we are no longer doing the
DR_SWAP in RO mode, this is mostly innocuous for a regular power-supply,
but this would break the docking use-case. Normally, we will do it as
soon as we have jumped to RW, so the dock should still work unless the
developer is using the machine with RO EC (eg EC development with
soft-sync disabled).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=reef
BUG=b:35648282
TEST=Boot Snappy without battery. Verify RO image doesn't swap
data roles and soft reset issued by RW image as SNK/UFP is
accepted by the HP adapter.
Change-Id: Id184f0d24a006cd46212d04ceae02f640f5bda65
Reviewed-on: https://chromium-review.googlesource.com/461142
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
Add new host command EC_CMD_RWSIG_ACTION for controlling rwsig task.
This allow us to make firmware stay at RO without toggling reset pin.
flashrom can use this host command and removed the need to use any
out-of-band pin to toggle the reset pin (and make RWSIG stay in RO).
BRANCH=none
BUG=b:37584134
TEST=on eve, `ectool --name=cros_tp rwsigaction abort` should prevent EC
from jumpping to RW after RWSIG check.
Change-Id: Ia435e4e3ea8ed612a1250d3bf755ca50e5db9d37
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497787
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Create an app to extract relevant information
from the EC code base that's used to create Vendor
Information Files (VIFs) needed for USB Type-C
compliance testing.
BUG=chromium:701852
BRANCH=none
TEST=make -j buildall
Compared generated VIFs to expected values
Change-Id: I600ca78b9fb5d2de78aa65a58264c6f79b36ea17
Reviewed-on: https://chromium-review.googlesource.com/455280
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Provide led_control API that can be used by different drivers to
control the state of LED (0=off, 1=on, 2=reset)
2. Add a new LED ID for recovery HW_REINIT indication.
BUG=b:37682514
BRANCH=None
TEST=make -j buildall
Change-Id: I27334bde2b879046746456a610208f3fc2dd68b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/487840
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The node locked ROs expect the RW image to be self signed with a 2048
bit key.
The only case where loader-testkey-A.pem file is used is is building
vanilla images which can't even run any more (they used to be good
for old dev RO). Let's replace the 3072 bit key with a 2048 bit key
generated by running
'openssl genrsa -3 2048 > util/signer/loader-testkey-A.pem'
BRANCH=none
BUG=none
TEST=verified that RW signed with this key can be run by a node locked
RO.
Change-Id: I74d189d03acb663fde7db48815e54748163c6399
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/489434
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This change is separated from CL:344481.
We need a cold reset after flashing, but we kill 'servod' before
execute iteflash for each flashing process.
With this change, we can restart 'servod' again without errors.
And we are able to use dut-control to do a EC cold reset.
BRANCH=none
BUG=none
TEST=flashing completed, and wait for servo's cold reset.
Change-Id: Ifc242467211253fabcd733a971e999baa68a1026
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/488002
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a new host command EC_CMD_RWSIG_CHECK_STATUS for getting rwsig
status and rw firmware hash. This command is used to check the RW
signature of newly updated RW image.
A new subcommand is also added to ectool.
BRANCH=none
BUG=b:37584134
TEST=on rose board `ectool rwsigstatus` works
Change-Id: I33d8709f5248d3a4b8bedb36ded84a93dc8c971f
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/485079
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
ecst adds the support for npcx7 series in this CL. (The name of npcx7m6f
is fixed. The others are TBD.) It also includes:
1. Fix few typos and replace tab with spaces in ecst.h for better
alignment.
2. Add -spiclkratio parameter for the ratio between core and spi flash
clock in npcx7. (default ratio is 1.)
3. Add -unlimburst parameter for burst mode of spi flash accesses.
(default is disable)
BRANCH=none
BUG=none
TEST=No build errors for npcx7 and npcx5 series. Build poppy board with
ecst 1.0.3 and upload FW to platfomr. No sympton found.
Change-Id: I004edc068c6496390e03d8ee5e39e4f23e4b835f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/476413
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The derivatives development should be done in the firmware branch.
(here it is firmware-reef-9042.B)
They are way too many 'follow reef settings' CLs, either all derivatives
should be updated at the same time or we have to cut the rotten fruits.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36192920
TEST=make buildall
Change-Id: I20cbc4897c7e6e3355ca0a4ed0e856d6b1d17eff
Reviewed-on: https://chromium-review.googlesource.com/452459
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We are still building two images - for prod and dev fused H1 chips.
This requires different pairs of RO images and calls for using
different keys when signing RW images.
Each produced image is of 512K bytes in size, the ROs are paced at
offsets 0 and 0x40000, the RWs at offsets 0x4000 and 0x4000.
The signed ROs come from their respective source, their processing is
limited to converting into binary format and verifying that their key
signatures match image designation (prod vs dev).
The RWs binaries are derived from RW elf files which are the result of
running 'make BOARD=cr50'. The elves are converted into binary format
and signed, the bs script is used for that.
The bs script is modified to accept the destination file name from the
shell variable, to detect signing failures (resulting in zero sized
binaries), and to fix error reporting.
The new script create_released_image.sh expects exactly six command
line parameters:
<prod RO A>.hex <prod RO B>.hex <dev RO A>.hex <dev RO B>.hex \
<RW.elf> <RW_B.elf>
and generates two cr50 binary images.
The generated images are placed in the directory named cr50.r<ro
vers>.w<rw vers> (the versions are retrieved from the binaries using
usb_updater), and then placed in the tarball with the same base name.
This naming convention is imposed by the ebuild pulling in the tarball
from the binary component server (BCS).
On the successful completion the script prints out commands which can
be used to upload the new tarball to the BCS.
BRANCH=none
BUG=b:35587234
TEST=ran the script to generate the r0.0.10.w0.0.18 release, verified
that all components of both imagea are properly signed (are
bootable and the key signature matches the prod/dev convention).
Change-Id: I87be1d44a721c979bdeeabf986d717e3a382db45
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439907
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
With the rest of support in place, this patch adds code which would
corrupt the headers received during firmware updates.
The VENDOR_CC_TURN_UPDATE_ON vendor command will be required to enable
the new images.
Care should be taken that other commands operating on the inactive
image header do not do anything with it before it was enabled, some
code is being added for that.
The minor RW version is being bumped up to 19 to clearly indicate that
the device is expecting the vendor command to enable the new image
(this is used by usb_updater when downloading the image without the -p
or -u command line options).
BRANCH=cr50
BUG=b:35580805
TEST=verified that the new image can be installed and started by the
new usb_updater.
- the inactive header after uploading with the -p option (the
image_size field's offset is 0x32c):
> md 0x84320 4
00084320: 00000000 00000000 80033800 00084000
rebooting the device does not start the new image.
- the inactive header after uploading without the -p option:
> md 0x84320 4
00084320: 00000000 00000000 00033800 00084000
the device running a DBG image reports the following in the end of
the image update:
[64.176780 FW update: done]
turn_update_on: rebooting in 100 ms
Change-Id: I4d763eb89c8b1a43a13697033201066779826e85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
tigertail allows muxing a usb-c port onto two different
passthough targets. This allows for automated switching
between USB host and device without DUT or endpoint knowledge.
tigertail also routes SBU lines to stm32 UART, and has INAs on
VBUS and VCONN to measure power.
BUG=b:35849284
BRANCH=None
TEST=Muxing power, muxing USB, uart works, INAs work.
Change-Id: I5bf2ba038aa78e59352ad99cd71efb0f0d0fbec9
Reviewed-on: https://chromium-review.googlesource.com/438677
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When invoking ectool fan commands on older ECs not supporting
EC_CMD_GET_FEATURES, the tool is choking on the lack of the command at
the beginning of get_num_fans() and not going further.
The regression was introduced by
https://chromium-review.googlesource.com/c/359069/, let's go back to the old
behavior for machines without feature bits and skip the
EC_FEATURE_PWM_FAN check.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35575890
TEST=on Buddy, run 'ectool pwmgetnumfans' and 'ectool pwmgetfanrpm all'
and get results.
Change-Id: Ie9255d4afc9fa95a55807c310e9593a28c2aadc1
Reviewed-on: https://chromium-review.googlesource.com/456598
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some people love to address the EC device nodes by number with ectool,
add the special offset for the FP MCU (e.g. '--dev=8').
Addressing it by name already works (e.g. '--name=cros_fp').
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, execute 'ectool --dev=8 version'
and see a similar result to 'ectool --name=cros_fp version'
e.g. "RO version: eve_fp_v1.1.6177-945b19f+ [...]"
Change-Id: Ic08e3b7a3ae31b7e1b73bccc8375badf3284b49c
Reviewed-on: https://chromium-review.googlesource.com/453179
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Erase the first location in the manifest info map to ensure that the
flash info state is updates and then the RO prevents booting earlier
images (where the map is unaltered).
BRANCH=cr50
BUG=none
TEST=verified that once both RW_A and RW_B are programmed with the new
image and the H1 is restarted, the first info map location is erased.
Change-Id: Id48d8a2009f7cf9842b7a33f036dc98457dbeafc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455580
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
