Add the evaluation board driver of npcx7 series ec for testing. If you
received the evb which ec is 128-pins package, please notice it has
the following limitations.
a. No GPIOD7/E0 pins.
b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports.
c. No ADC7, ADC8 and ADC9 channels.
d. No JTAG port 1.
e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb.
This CL also includes:
1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg.
Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ.
2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl.
3. Add npcx7_evb support in flash_ec.
BRANCH=none
BUG=none
TEST=Passed all npcx7 drivers verification on the evb no matter which
ec's package is 128 or 144 pins package.
Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since npcx5m6g has larger than 128 KB code ram for FW, the original
alignment between RO & RW regions isn't suitable for new chip.
Therefore, we add 256KB alignment of them for npcx5m6g.
In order to program the flash used by npcx5m6g, we add new board array,
BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout
ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g
and flash_npcx5m6g to program flash with different layout.
Modified sources:
1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for
npcx5m6g.
2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to
distinguish which flash layout ec used.
3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with
different layout.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/331903
Reviewed-by: Shawn N <shawnn@chromium.org>
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
All boards in ToT have the same RO configuration.
Boards which define CONFIG_FLASH_PSTATE_BANK have pstate following RO.
BRANCH=none
BUG=chrome-os-partner:22990
TEST="git grep" to see that none of the affected functions are called.
Change-Id: Ie1eb9a726e1fa157852b0c55d474c9b4587c41f0
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273908
Reviewed-by: Randall Spangler <rspangler@chromium.org>
rename setup_openocd -> flash_openocd
refactor so that flash_npcx and flash_lm4 set OCD_CMDS and call flash_openocd
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after and compare the sequence of calls to
dut-control and the command-line args to openocd
tested with ryu (non-lm4), samus, link, npcx_evb, and peppy
Change-Id: I7a05e3219d4b324bcf19a20f86b149f8e3377465
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273907
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Avoid duplicating servo configurations for every chip.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=None. This is an intermediate step to make it clear what's happening.
CQ-DEPEND=CL:273950
Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273906
Reviewed-by: Randall Spangler <rspangler@chromium.org>
