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flash_ec: add support for SWD, nrf51, and hadoken

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BUG=none
TEST=manual
BRANCH=none

flash_ec --board=hadoken
flash_ec --board=npcx_evb
flash_ec --board=samus

Use openocd in SWD mode to flash the nRF51 chip.

Use warm_reset to exit DEBUG mode.

Change-Id: Iaf2827d4ce5be6d61431a3de7ab4f86aa4adde02
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287039
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Myles Watson
2015-07-17 13:05:43 -07:00
committed by ChromeOS Commit Bot
parent d804e8fdbd
commit 050db0510e
6 changed files with 71 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
util/flash_ec
View File

@@ -85,6 +85,10 @@ BOARDS_NPCX=(
npcx_evb_arm
)
BOARDS_NRF51=(
hadoken
)
BOARDS_MEC1322=(
cyan
glados
@@ -403,6 +407,16 @@ function flash_lm4() {
}
function flash_nrf51() {
OCD_CHIP_CFG="nrf51_chip.cfg"
OCD_CMDS="init; flash_nrf51 ${IMG} ${FLAGS_offset}; exit_debug_mode_nrf51; shutdown;"
flash_openocd
# waiting 100us for the reset pulse is not necessary, it takes ~2.5ms
dut_control swd_reset:on swd_reset:off
}
function flash_npcx() {
IMG_PATH="${EC_DIR}/build/${BOARD}"
OCD_CHIP_CFG="npcx_chip.cfg"
@@ -486,6 +500,8 @@ elif $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then
CHIP="stm32_dfu"
elif $(in_array "${BOARDS_NPCX[@]}" "${BOARD}"); then
CHIP="npcx"
elif $(in_array "${BOARDS_NRF51[@]}" "${BOARD}"); then
CHIP="nrf51"
elif $(in_array "${BOARDS_MEC1322[@]}" "${BOARD}"); then
CHIP="mec1322"
elif [ -n "${FLAGS_chip}" ]; then

7
util/openocd/lm4_chip.cfg
View File

@@ -1,4 +1,11 @@
ftdi_layout_init 0x0018 0x009b
# open collector oe only
ftdi_layout_signal nSRST -oe 0x0020
reset_config trst_only
source [find target/stellaris.cfg]
source [find lm4x_cmds.tcl]

7
util/openocd/npcx_chip.cfg
View File

@@ -2,3 +2,10 @@
source [find npcx.cfg]
source [find npcx_cmds.tcl]
ftdi_layout_init 0x0018 0x009b
# open collector oe only
ftdi_layout_signal nSRST -oe 0x0020
reset_config trst_only

14
util/openocd/nrf51_chip.cfg Normal file
View File

@@ -0,0 +1,14 @@
#nRF51 uses SWD
transport select swd
# Since nTRST is repurposed, we need a different layout_init setting
ftdi_layout_init 0x0008 0x009b
ftdi_layout_signal SWDIO_OE -nalias nTRST
ftdi_layout_signal SWD_EN -alias TMS
#Disable fast flashing, it only works with ST-Link and CMSIS-DAP
set WORKAREASIZE 0
source [find target/nrf51.cfg]
source [find nrf51_cmds.tcl]

22
util/openocd/nrf51_cmds.tcl Normal file
View File

@@ -0,0 +1,22 @@
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Command automation for Nordic nRF51 chip
proc flash_nrf51 {path offset} {
reset halt;
program $path $offset;
}
proc unprotect_nrf51 { } {
reset halt;
nrf51 mass_erase;
}
# enable reset by writing 1 to the RESET register
# This will disconnect the debugger with the following message:
# Polling target nrf51.cpu failed, trying to reexamine
proc exit_debug_mode_nrf51 { } {
mww 0x40000544 1;
}

8
util/openocd/servo.cfg
View File

@@ -6,7 +6,9 @@ gdb_flash_program enable
interface ftdi
# VID/PID for servo v2, servo v3
ftdi_vid_pid 0x18d1 0x5002 0x18d1 0x5004 0x18d1 0x500d
ftdi_layout_init 0x0c08 0x0f1b
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
# Only initialize Port A
ftdi_channel 0
# unbuffered connection data == oe
ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010