After firmware update, cr50 toggles the EC's reset line, expecting
the system will boot. This isn't the case for Chromebox because it
sets AP_OFF flag on a clean shutdown (to restore the previous power
state after power loss & restore).
This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot
command. It makes EC first clear AP_OFF then hibernate.
BUG=b:69721737
BRANCH=none
TEST=Verify Fizz reboot after cr50 update.
Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EC_IN_RW signal is used to determine if the switch to dev mode can be
safely made. However, EC_IN_RW needs the EC_RST_L line driven low in
order to be reset. In faft tests that utilize crosEcSoftrecPower
method, EC_RST_L is not being driven by servo to fix other test
failures related to keeping EC and AC reboots in sync.
This CL adds a new argument 'wait-ext' to the EC reboot command.
When this option is used, instead of the EC generating a reset via
it's system watchdog, it will wait 10 seconds for EC_RST_L to be
driven.
BUG=b:64603944
BRANCH=coral
CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b
TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode"
mutliple times and verified that it passes. Previoulsy, this test
always fails when the EC is in RW before it starts. Also tested
platform_ServoPowerStateController_USBPluggedin and verified it passed.
Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/737524
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the host sets rtc alarm wake time = 0, it wants
to reset and disable the alarm.
Also, align the implementation in npcx with that in stm32
to check both delay_s and delay_us.
BUG=b:66971951, b:63908519
BRANCH=none
TEST='ectool rtcsetalarm 3'. After alarm goes off, run
'ectool rtcgetalarm' and then see 'Alarm not set'.
Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/691256
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
In the CL:505861, we print the warnning message to indicate that the VBAT
has ever dropped if the IBBR bit is set but do not clear the IBBR. This
forbid the access to BBRAM until EC power-on reset.
In this CL, we clear the IBBR bit to make BBRAM work again without the
need of EC power-on reset.
BRANCH=none
BUG=none
TEST=No build error for make buildall; Check warining messages are
printed and IBBR bit is cleared.
Change-Id: I58a0370c1c496b3c1208d9d5ac6b55c4d66fe8b6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/542976
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes EC read the slot to verify and jump to from the
battery backed up RAM (BBRAM).
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz
Change-Id: I0c78861ea3ccdc45d0aa08e690e3a68f53658409
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/518255
This patch sets/clears RESET_FLAG_AP_OFF on S5<->S3 transitions.
It's set when the system gracefully shuts down and cleared when the
system boots up. The result is EC tries to go back to the
previous state upon AC plug-in on battery-less systems.
This is required for digital signage and kiosk.
This also reverts: CL 514209, 486946, and 486945.
BUG=b:37536389
BRANCH=none
TEST=Tested as follows:
A. Boot to S0
A.1. Unplug AC while system is in S0 then plug in - PASS
A.2. Unplug AC while system is in S3 then plug in - PASS
A.3. Press recovery+power in S0 - PASS
A.4. Press recovery+power in G3 - FAIL (To be fixed)
A.5. Execute reboot console command - PASS
A.6. Execute reboot OS command - PASS
A.7. Execute reboot console command in G3 - PASS
B. Boot to G3
B.1 Unplug AC while system is in G3 then plug in - PASS
B.2 Unplug AC after B.1 then plug in - PASS
B.3 Shutdown by power button on recovery screen then unplug
plug in AC - PASS
B.4 Execute reboot ap-off console command - PASS
B.5 Execute shutdown command from OS then plug in AC - PASS
Change-Id: Iaa6f930585050fdd3511c711b449dff47525066d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This CL adds:
1. Fixed the incorrect address of BKUP_STS register.
2. Cleared the IBBR bit of BKUP_STS register at initial because
its default value is 1(means the content of BBRAM is invalid) whenever
VBAT is powered up.
3. Add debug msg when IBBR bit is set to indicate the BBRAM's
corruption.
4. Modified the valid BBRAM offset from 1 to 0 and size from 63 to 64.
BRANCH=none
BUG=b:38187362
TEST=No build error for make buildall; Check IBBR is cleared at initial.
Check IBBR is set by changing the VBAT voltage below VBAT MIN.
Test console command "reboot ap-off" on poppy.
Change-Id: I69d98b50d4e0aec17b55a4a9b5e8f1a412a3fe45
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505861
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In old system driver, ec clears "Predefined Time Occurred" (PTO) flag
before setting a new alarm (PT field in WTC). If PT field is the same
as the first 25 TTC bits at this moment, we might receive unexpected
rtc interrupt again. This CL sets new alarm first then clears PTO flag
to make sure rtc interrupt is issued from new alarm.
BRANCH=none
BUG=b:38310685
TEST=Duplicated the same symptom by the script in issue 38310685 on
gru. No symptoms occurred with the same script for 3 hours by applying
this CL.
Change-Id: Ia6410d6aa4ef8e2acb7bfadf9192d619045bfa58
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/508572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add generic routines to read or write a byte to battery-backed RAM, and
implement vbnvcontext get/set using these routines.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, with subsequent commit, run "cutoff" on the console,
reattach AC, and verify device successfully wakes. Also verify Rp is
dropped on console 'reboot' and F3 + power from RW.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d
Reviewed-on: https://chromium-review.googlesource.com/444444
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add and export chip_save_reset_flags to allow boards to use this
function when required.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Compiles successfully for poppy.
Change-Id: I6f96bc61135fc4e3abb62a01d47c2cba8eb45b60
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Similarly to eve, we have a problem where the EC is not able to
distinguish between power up and reset, as VCC1_RST is simply
tied to PP3300_DSW.
BRANCH=none
BUG=chrome-os-partner:61028
BUG=chrome-os-partner:61930
TEST=Press Power+Volume Up+Volume Down, poppy enters recovery
Change-Id: Id0d89b56058e288c14e10eee7656965eee75047a
Reviewed-on: https://chromium-review.googlesource.com/428532
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The EC on Eve has VCC1_RST connected to 3.3DSW which drops when
resetting for recovery.
Since I need this to work on current boards treat Eve the same as
Wheatley and use the workaround that always reports reset-pin
instead of power-on status.
BUG=chrome-os-partner:61028
BRANCH=none
TEST=successfully enter recovery mode on eve with the keyboard
Change-Id: Ica583d9a95d78689ee1b21ccfa882fced2a414d9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421128
Reviewed-by: Shawn N <shawnn@chromium.org>
Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO
states to ROM POR values. Therefore, it is necessary to re-init GPIO
states once again based on board-level GPIO settings.
BUG=chrome-os-partner:58077
BRANCH=gru
TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify
actual register values are printed rather than zeros.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717
Reviewed-on: https://chromium-review.googlesource.com/395426
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
NPCX reboots by triggering the watchdog which in turn causes
the watchdog reset flag to be set as one of the system-wide
reset_flags. However, other software can confuse the presence
of the watchdog reset flag as a panic.
This patch selectively sets the watchdog reset flag only if we're
not explicitly doing a soft or hard reset or waking from hibernate.
Patch created by Mulin Chao <mlchao@nuvoton.com>
BUG=chrome-os-partner:56594
BRANCH=none
TEST=panic reset no longer observed
Change-Id: I016b59ffda4f6334cf41e196960edcbb87f6c049
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds a function that allows the real-time clock to be
printed on the EC console. This could be helpful in trying to correlate
events between the EC's log and the kernel's.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=make -j buildall
Change-Id: I5e20692a173bddea3dc5c20cc0f2061cc170ce7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388856
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We found the api utility in ROM doesn't enable burst mode of GDMA. It
influences the performance of FW download a lot. The CL modified GDMA
for moving the code of the other region from flash to ram. And move a
function that kicks off GMDA transactions to suspend ram in case this
utility is erased by itself. This issue will be fixed in our next
generation.
Modified sources:
1. system.c: Implement GDMA bypass.
2. system_chip.h: Import flash addresses for GDMA bypass code.
3. registers.h: Add GDMA register definitions.
4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script.
BRANCH=none
BUG=chrome-os-partner:56794
TEST=make BOARD=npcx_evb; test sysjump and measure download time
Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381779
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
TTC must be written twice, otherwise the value will be lost on EC reset,
even if VBAT stays stable.
BUG=chrome-os-partner:57010
BRANCH=None
TEST=On kevin, run 'rtc set 55555' then trigger cold reset through
servo. Run 'rtc' on subsequent boot and verify timing ticks did not
reset to zero.
Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382654
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In order to improve the performance of sysjump, the CL increases the clock
freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps
into the other region successfully, the clock freq is restored to the
default value (15MHz) in main routine.
Modified sources:
1. clock.c: Add clock_turbo for speed up clock's freq to max.
2. clock_chip.h: The declarartion for clock_turbo.
3. system.c: Speed up clock rate before downloading FW.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers
Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is necessary after the pending patch to not enable all GPIO
interrupts by default.
BRANCH=None
BUG=chrome-os-partner:56486
TEST=Manual on kevin, run 'hibernate', attach AC and verify wake occurs.
Change-Id: I04d2c6edf9fb32b1a6a7e6a5ed4d2c53895e00f0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374179
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Although probability is small, we still have chance to encounter the same
symptom which CPU's behavior is abnormal after wake-up from deep idle.
Apply the same bypass in task.c but not enable interrupt to solve it.
Modified sources:
1. system.c: Apply deep idle bypass for hibernate.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; test "hibernate"&"hibernate 10" on wheatley.
Change-Id: Ib00b9932ac34414d6a177d60668664ab31284a79
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/373300
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Remove "task_disable_irq()" function call in EC_RTC_ALARM_CLEAR case.
Host command "RTC_SET_ALARM" with 0 second does not disable volume key interrupt.
BUG=chrome-os-partner:55401
BRANCH=none
TEST=check EC UART log message.
If you press volume up/down button
- Before HC 0x47 (RTC_SET_ALARM Command with 0 second)
Log : Button 'Volume Up/Down' was released.
- After HC0x47
Log : Button 'Volume Up/Down' was released.
GPIO volume key is still enable.
Change-Id: I8d8a4fa4927046b76a49ac4833b6a710db2e05be
Signed-off-by: younghun kim <young-h.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/361670
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Younghun Kim <young-h.kim@samsung.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Adding ability to get # seconds before rtc alarm
goes off.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=ectool rtcgetalarm w/o setting returns
Alarm not set.
ectool rtcsetalarm 30; ectool rtcgetalarm
to make sure counting down to 0. After alarm
goes off, rtcgetalarm should return alarm not
set again.
rtcsetalarm 30; rtcgetalarm to check alarm is set.
rtcsetalarm 0; should disable alarm. Use
rtcgetalarm to ensure that alarm is disabled.
Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353331
Reviewed-by: Shawn N <shawnn@chromium.org>
We have no guarantee about the alignment of our input buffer so don't
use 32-bit access.
BUG=chrome-os-partner:54561
BRANCH=None
TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't
encountered on host command 0x17. Also verify call to
system_set_vbnvcontext followed by system_get_vbnvcontext results in
same data being read back.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351
Reviewed-on: https://chromium-review.googlesource.com/354132
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Only way to set alarm previously was through
rtcalarm command on EC console. Implemented
interface through ectool so that the AP can set
it as well.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=from AP console, run ectool rtcalarm <sec>
Should see [event set 0x02000000] from EC
console in approximately <sec> seconds.
Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347493
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Previously the keyboard row and column pins could not use the GPIO
alternate function mechanism because their DEVALT bits were inverted
with respect to all of the others, making it impossible to correctly
configure them. With the refactor of the GPIO driver we can now add
the keyboard DEVALT entries to the gpio_alt_table, and use the
ALTERNATE macro and associated APIs to control the keyboard pin states.
The Wheatley RO firmware image is still 320 bytes smaller than before
the GPIO refactor.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Ran on Wheatley, manually verified keyboard functionality
Change-Id: Id04bc010834b5d95050b03ace6b0e1c5690757bf
Reviewed-on: https://chromium-review.googlesource.com/329762
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
board_hibernate() may take alternate actions to place the chip into
hibernate, so inform the PD MCU that we're going to hibernate before
calling the function.
BUG=None
TEST=Run 'hibernate' on chell, verify that PD MCU goes to hibernate and
wakes when AC is attached.
BRANCH=glados
Change-Id: I71c12dcb416d54c79ac7d40e9bf430e268071fb2
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327613
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow boards to take action (such as entering a custom low-power
hibernate-like state) before putting the chip into hibernate state.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual with subsequent commit on chell. Verify board-level
hibernate callback is called when "hibernate" is run on EC console.
Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324086
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The new gpio_reset function simplifies the pattern used in this code,
that of returning a GPIO to its original configured state. It also
removes a few instances of using port/mask pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d
Reviewed-on: https://chromium-review.googlesource.com/324059
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L
and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs
simultaneously since EC's power rail is turned off by PMIC for a while.
VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery
mode detection.
The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset.
Use BOARD_WHEATLEY to distinguish them.
Modified drivers:
1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I96198ffb6901f0539755046ca303e94381ae7541
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320641
Reviewed-by: Randall Spangler <rspangler@chromium.org>
