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4 Commits

Author SHA1 Message Date
Gwendal Grignou
2590ce9538 common: Add software CTZ implementation when needeed 
CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or
nds32.

Used in ST sensor drivers.

BUG=none
BRANCH=none
TEST=compile

Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/767609
Commit-Ready: Ely Vazquez <nadia198877@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
 2017-11-16 23:32:11 -08:00
Bill Richardson
104f811e67 cleanup: fix all the header guards 
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.

BUG=chromium:496895
BRANCH=none
TEST=make buildall -j

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
 2015-06-18 19:07:00 +00:00
Shawn Nematbakhsh
d008477824 cortex-m*: Save panicinfo on non-exception panics 
Make non-exception "software" panics such as stack overflow and assert
failure save a panic log. Log the panic type in r4, and misc. panic data
in r5 so that panic reasons can be distinguished.

BUG=chrome-os-partner:36744
TEST=Manual on samus_pd. Run 'crash divzero' then 'panicinfo' after
reboot. Verify that panic info is printed with "r4 :dead6660". Trigger
stack overflow, verify that panic info is printed with "r4 :dead6661".
BRANCH=Samus

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I5f7a8eb0a5c2ac5799d29bb241deb24fabf38f68
Reviewed-on: https://chromium-review.googlesource.com/249912
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
 2015-02-18 04:53:51 +00:00
Vincent Palatin
0f73a129b4 Add Cortex-M0 core support 
The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.

Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
 2014-03-11 05:52:41 +00:00