This is set when the EC boots and sees the recovery key combo.
This is preferable to the memmap'd keyboard recovery switch, which the
host has no way of clearing. The idea is that the host RO firmware
reads this event and sets the recovery reason.
I will be removing the memmap'd keyboard recovery switch once U-boot
and coreboot check this new event.
BUG=chrome-os-partner:10034
TEST=manual
1. power+esc+refresh; should see this even in EC log
[0.000838 event set 0x00004000]
(time of event may vary)
2. reboot EC; should NOT see the event
Change-Id: Id0672749f63c5022624a72ec91d30dcadfea5ef8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27328
Now both copies of the event state live in host_event_commands.c, and
lpc / memmap just shadows the main copy.
BUG=chrome-os-partner:11172
TEST=manual
Boot system. should see events 0x2000, 0x80, 0x08 get set and then cleared.
At U-boot prompt, type on keyboard. Should set event 0x1000 get set,
but only on the first keypress (because U-boot doesn't consume that
event).
Then from EC console,
hostevent clear 0x1000 -> see event 0x1000 clear
hostevent clear 0x1000 -> no debug output (it's already clear)
hostevent clearb 0x1000 -> see event copy B 0x1000 clear
hostevent clearb 0x1000 -> no debug output (copy B is already clear)
Change-Id: I855c035865649ba1490cd9027157d5bcdcc9895f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27321
Both EC and ectool are still backwards-compatible to the old interface.
BUG=chrome-os-partner:11275
TEST=manual
From U-boot prompt: mkbp hash // test old host talking to new EC
From root shell: ectool echash // test new host talking to new EC
You can also update just the OS and use an old EC, and verify that
'ectool echash' still works, which tests a new host talking to an old
EC.
Change-Id: I2afbb208cb16836f842ba119b74b1ab6a38ce5d5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27313
Saves 2 params being passed around needlessly.
BUG=chrome-os-partner:11275
TEST=mkbp hash from u-boot console should still work
Change-Id: I958e4a09f16413e4d051e278dc0384aa9b791aa4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27312
And retain compatibility for old requests.
BUG=chrome-os-partner:11275
TEST=from u-boot prompt, 'mkbp hash'
from root shell, 'ectool flashread 0 68084 /tmp/foo'
then compare to first 68084 bytes of ec.bin
Change-Id: Id82068773703543febde79fc820af7486502e01f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27226
This is necessary for an imminent change which passes version data
from the host bus (LPC/I2C/SPI) into the host command handler.
BUG=chrome-os-partner:11275
TEST=from u-boot prompt, 'mkbp hash'
Change-Id: If34d0d7c6dc320ad5632becf512c30900fd61aca
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27190
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Added version mask field to DECLARE_HOST_COMMAND() because it's
convenient to do so when I'm touching all host command
implementations, but all commands simply declare version 0 and nothing
checks it yet. Will add version support in a followup CL.
This change is internal to the EC; it does not change the data sent
over the host interface.
BUG=chrome-os-partner:11275
TEST=manual
ectool version && ectool echash; should get sane data from both
ectool flashread 0x80 0x40 /tmp/foo && od -tx1 /tmp/foo
should match data from offset 0x80 of ec.bin (od -j128 -n64 -tx1 ec.bin)
Change-Id: I5699f72b8d5e1ac23929353c9a34158d76c44206
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27172
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change shorten the timeout period to 10ms.
Experiments showed that most master mode communication status bit
changed within 2000us. Hence 10ms timeout is much reasonable than
the original value.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=none
TEST=manual, with i2c scope
Change-Id: Ib26795bd2e4877b5c33719e96a2c2c7c11333eab
Reviewed-on: https://gerrit.chromium.org/gerrit/27145
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Now that ACPI events are handled directly in the LPC interrupt
handler, we can simplify the host event code.
BUG=chrome-os-partner:11240
TEST=boot system; should boot
close lid; should send SMI and suspend system
Change-Id: I8c73ea31a66e94310e4460a008635a103220413e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27100
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
And only support it for port 62/66.
Also remove 'ectool queryec', because it can't touch port 62/66 once
the kernel/ACPI owns it, and query-event isn't supported on the user
command port.
BUG=chrome-os-partner:11240
TEST=boot system and check EC console output; should see event clears between
host commands 0x23, 0x8e, but no hostcmd 0x84.
[0.396780 LPC RESET# deasserted]
[0.486953 Port 80: 0x29]
[0.487415 hostcmd1 0x23]
[0.764407 Port 80: 0x88]
[0.764579 event clear 0x00000008 -> 00002080]
[0.764928 event clear 0x00000080 -> 00002000]
[0.765224 event clear 0x00002000 -> 00000000]
[0.765578 hostcmd1 0x8e]
[0.765868 hostcmd1 0x06]
Change-Id: I8ed161dbccd396d685ddf6829a27dfef87d919fb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27095
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
BUG=chrome-os-partner:9922
TEST=manual
Press power+refresh+d.
From ec console, 'optget'. No reference to fake dev switch
From host, 'ectool vboot'. Should see either 'fake_dev=0' or no mention of fake dev switch at all.
Change-Id: I66bc5e926d6e639b206563e764bcc730cce9227c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27061
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This fixes a small bug introduced in a previous refactoring CL where
by the data buffer offset wasn't being incremented, thus causing
writes to repeatedly write the first two bytes of the incoming data
to each chunk of memory.
BUG=chrome-os-partner:11097
TEST=successfully wrote and verified data on Snow
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I8dae00652f4d74bc6ef449297b6e78b13b21255f
Reviewed-on: https://gerrit.chromium.org/gerrit/26985
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
When debug port is left unconnected, EC get garbage keypress input from
both UART ports due to UART pin floating. By clearing UART receive FIFO
when initializing UART module, this can be prevented.
BUG=chrome-os-partner:10235
TEST=Reset EC with debug port unconnected. Check u-boot doesn't get any
keypress.
Change-Id: I3e84db1f2f95a0173c11180f6afb3edb705d0ae5
Reviewed-on: https://gerrit.chromium.org/gerrit/26908
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
If the 'percent' passed in is lower than 0, then set it to 0. If it is
higher than 100, set to 100.
BUG=chrome-os-partner:11052
TEST=Check with 'kblight', 'fanduty', and 'faninfo'.
Change-Id: If84ab12658bf136eaaf1adecc0522a977c94f98d
Reviewed-on: https://gerrit.chromium.org/gerrit/26904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Also add new 'invalid' host event bit; if the host reads this, it
knows the memory-mapped data for current events is invalid.
BUG=chrome-os-partner:11146
TEST=manual
On host, ectool eventget -> should print events = 0
On EC, hostevent set 0x80000000
On host, ectool eventget -> should print events = invalid
Reboot EC; should see debug output where event mask 0x2000 is set
during the boot process.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I8d3f161eec25db50ac06e3642a1a1fb8edb9590e
Reviewed-on: https://gerrit.chromium.org/gerrit/26876
512 bytes isn't enough to capture all the debug output early in the
init process, and Link EC has lots of unused RAM. stm32 doesn't, so
only do this for LM4 processor.
BUG=none
TEST=build; debug output during init shouldn't be garbled
Change-Id: Ie4fd204fa4e0c6ca99ea7eae94b095ef175836e4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26877
If we don't store PWM module state, fan would be disabled after system
jump until the next reboot. Let's preserve fan and keyboard backlight
state.
BUG=chrome-os-partner:11027
TEST=Boot and "sysjump a". Check fan is still enabled.
Change-Id: I57dbcabef79264af7fcedb8fa0c00ff6299b97d5
Reviewed-on: https://gerrit.chromium.org/gerrit/26757
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:11090
TEST=suspend laptop, then press power button; should resume from suspend
Change-Id: I36b7c62b2e115bb97d37defcd3c783af0f91d5f8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26730
And fix returning memory-mapped string length on LPC as well.
BUG=chrome-os-partner:11090
TEST=manual
from EC, 'hostevent set 0x40000'
from host, 'ectool eventget' --> should print 0x40000
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I9edbd0a1468b5d4160ce67c471332226e51fa868
Reviewed-on: https://gerrit.chromium.org/gerrit/26719
Reviewed-by: Simon Glass <sjg@chromium.org>
There are a lot of timeous in the i2c driver. When one occurs, print
out the number of it so that the root cause can more easily be
examined.
BUG=chrome-os-partner:10888
TEST=manual:
Lock up the i2c bus from the AP by running the kernel without bus
arbitration doing i2c traffic:
while true; do i2cdump -f -y 4 0x48; done >/dev/null
and using 'pmu 100' on the EC.
Then see that a timeout error is printed, for example:
i2c wait_status timeout type 2, 101387 us
Change-Id: I3fb3fcf9f07966ef4e71d4358c791fea90aba5d5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26830
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The power button module now needs to know whether the chipset is in
the on state at init-time, in which case it doesn't need to send a
power button pulse to the chipset.
BUG=chrome-os-partner:11085
TEST=manual
1. power on AP to BIOS screen (e.g., in recovery mode)
2. At EC console, 'sysjump A'
3. system should stay powered on
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: Ic1f509204f502d1ddf87314f0e1582c21c991156
Reviewed-on: https://gerrit.chromium.org/gerrit/26700
Reviewed-by: Simon Glass <sjg@chromium.org>
We see some intermittent failure on PECI read. This CL lower PECI baud
rate from 150K to 100K. Also, we poll PECI temperature 4 times per
second and average over last 4 values. We only report read error when
last 4 read all fails.
This CL also increases the external path delay, increases retry count,
and also enable timing negotiation error bypass.
BUG=chrome-os-partner:10382
TEST=Still able to read from all temperature sensors
Change-Id: I38cefeabd9e3eff4bb8e4df4138c4ffd49cd84a2
Reviewed-on: https://gerrit.chromium.org/gerrit/26554
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
The current gpio_get_level() is pretty slow because it looks things up each
time. Add a new function to find out the register address and mask to use
to check the value for a particular GPIO.
Time-critical code can then use this to check a GPIO.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow;
Power on the board, hold power button for 10s and see that it powers off
Power control still works, thus GPIOs are functional
Change-Id: Ifc6c56f5cb811e0243e7712725a51948eabd42ab
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26175
Sometimes it is useful to get access to the flash directly, without using
flash_read(). Add a function to do this.
Since the range checking is done in every function in flash_common,
use the new function to do it for us. That way we get a slight (64 byte)
code size reduction.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow with SPI flash emulation, in U-Boot:
See that the 32KB of flash has been provided correctly.
Change-Id: I6622a24234edaed371dd5b9bf43d1f3974d55e39
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26174
The WWDG is not ideal for this purpose, since if we fail to handle its
interrupt withint 60ms or so, we get a reset. This can be a problem when we
are reporting a panic, since the uart output takes a long time.
Change to using timer 9, which is free, and make it print a watchdog warning
after one second.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow; waitms 1200 and see that a watchdog timeout is
reported correctly.
See that the panic message is displayed in full without a reset happening
before the end.
Change-Id: Ifc3671098e1f3a7ef409b8d1fb919d22eaa90358
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26172
This driver was not refactored when the host_command changes were made,
although i2c was. Tidy this up.
SPI requests the command response immediately rather than going through
the task queue, since otherwise a response may take long enough that the
SPI master misses it altogether.
BUG=chrome-os-partner:10533
TEST=manual:
build and boot on snow; In U-Boot:
> sspi 4:0 240 20
See that it gets key messages back now
Change-Id: Ia2c24d4c8876fefedad4c02802f77e50d7159d03
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25982
Use two suitable GPIOs to implement a simple arbitration scheme.
Each side owns one of the GPIOs, which are normally pulled high.
When one side wants to use I2C as a master, it pulls its GPIO low,
waits for a short period to make sure that the other side is not
also pulling its GPIO low, and then goes ahead with the transaction.
When the transaction is over, the GPIO is released, thus freeing the
I2C bus up for use by the other end.
For simplicity the terminolgy used here is EC for us, and AP for the
other end.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I97d9fbd5aba8248c8c1240baaec17db22860665c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26142
This corrects a small bug where by the UG bit in EGR was
not getting set, so the shadow registers were not being
reloaded as the comments suggest they should be.
This is really only a minor clean-up. The timer appears to
work fine with or without the patch.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=timerinfo appears sane on Snow
Change-Id: I637e2fc1f5dbfa1e70d33f96c8bf38ac57cc7b2c
Reviewed-on: https://gerrit.chromium.org/gerrit/26520
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Simplify this code, so that it does only one pass of the response data,
calculating the checksum as it copies.
BUG=chrome-os-partner:10535
TEST=manual:
build for all boards
build and boot on daisy
see that keyboard still works
Change-Id: I8b0a2ce1632dd4c1ff54736fb636d9a5cf8c9214
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25981
This seems to be a hangover from the LPC protocol. We can send a result
just by sending a response with no data.
Drop this function and remove all uses of it.
Also use 'enum ec_status' instead of int, since this is the correct
response type.
BUG=chrome-os-partner:10533
TEST=manual:
build for all boards
build and boot on daisy
Change-Id: I93a029bd6ba8cec567b61af3b410bcead015b5c0
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25980
This drives the power LED for Snow (PB3) using TIM2 in PWM mode.
Since timer setup and manipulation is STM32-specific, the power LED
logic moved to to chip/stm32/power_led.c.
This also adds a "powerled" console command for testing.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:10647
TEST=Tested on Snow with powerled command, compiled for Daisy
Change-Id: I5a7dc20d201ea058767e3e76d54e7c8567a3b83c
Reviewed-on: https://gerrit.chromium.org/gerrit/26267
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Add a new function to dump the current dma state, and hide it behind
a more official-sounding CONFIG_DMA_HELP.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: I42fb101628e9044284a6b39447b0b1fc2d36587b
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26168
By subtracting the current dma count from the number of bytes originally
requested to be transferred, we can find out how many bytes have been
transferred so far.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: Ideee1ed27c08b56882f5d2095341fe04bbe9c34b
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26167
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This change fixes mutiple snow charging issues. Including:
- disable i2c host auto selection
- i2c_read8 got wrong output value
- pmu CHARGE_EN control workaround
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:11010
TEST=Only test on snow dvt with AP turned off
plug/unplug ac adapter and check charging led
check console command 'battery'
Change-Id: I29d554b3daa4cfc538bd5bf5ba5233976d381861
Reviewed-on: https://gerrit.chromium.org/gerrit/26529
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chain TIM3/4 as the 32-bit timer instead of TIM2/3. This frees
up TIM2 to be used for other purposes.
BUG=chrome-os-partner:10647
TEST=Flashed onto Snow, stuff works and timerinfo output is sane
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Icdfe3596a15bc2ee8536f160b1f08ac3041b9193
Reviewed-on: https://gerrit.chromium.org/gerrit/26202
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add a way for boards to permit or deny access to the I2C port. This
works in a board-specific manner.
All I2C master traffic requires that board_i2c_claim() be called
first. A dummy function is provided for boards which do not require
this.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I786d4ae17f1d798faf13b303b5389679fb6720cb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26141
This allows us to prepare a dma transaction in advance, and quickly
start it when needed.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: Ib7d843b2d3a5cd94b6025b9741db1794ebbcfda0
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26449
This reverts commit 7af4172be4afad9d576549721a82b3a47d701647 / Iac605b879b3556f33af5585b298ada6bc4f52c90.
This change bypassed the commit queue and broke daisy as a result.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I7a05ab42f71a901d167bde977f8a025c7ef62dfc
Reviewed-on: https://gerrit.chromium.org/gerrit/26379
Reviewed-by: David James <davidjames@chromium.org>
Tested-by: David James <davidjames@chromium.org>
This allows us to prepare a dma transaction in advance, and quickly
start it when needed.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Iac605b879b3556f33af5585b298ada6bc4f52c90
Reviewed-on: https://gerrit.chromium.org/gerrit/26166
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Rather than a channel number, use a pointer. Also we don't need a
return value, since this function cannot fail.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: I9d7e567a9f3d496184fd28f0820ad798b1c43a28
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26165
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Access to dma is currently via a channel number. It is more efficient
to export a pointer to the dma channel since it avoids the conversion
on every API call. This helps, because dma is often on the critical
path.
Export the function to provide a pointer to a dma channel given its
number.
BUG=chrome-os-parter:10533
TEST=manual: build for all boards
Change-Id: I0318e59dbb1b9077f0445804692ca7ea99cf6581
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26164
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is ~4x as fast as flashing the entire EC image, and is similar to
the existing flash_link_a command.
BUG=none
TEST=from openocd prompt, flash_link_ro
Change-Id: I04160af3d7d70028f8d2789480094c283a1ce2ab
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26268
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
At present there is quite a bit of duplicated code. Create a new
i2c_transfer() function to take care of this.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I3672cc4ff9de4e2e0deaec2997590ee892ef09aa
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26140
