Original code doesn't handle those 2 commands well. SETREP needs a new
state for incoming data byte. EX_SETLED expects 2-byte parameter instead
of 1-byte.
Also enclose all asynchronous debug output in [] for servo-based testing.
BUG=chrome-os-partner:8674
TEST=on the target board. No "Unsupported data 0x00" message is seen.
Change-Id: Icb8e592fe54620677878ee15ef8a781c8906063e
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
Comapre the range to be write (erase) with the range of active image.
If overlap, return error to indicate the access denied.
Note that we actually protect only runtime code and ro data.
FMAP is intentional unprotected so that flashrom can update to new map
before jumping. Since the vector table and init code are in the same
erase page, they are unprotected as well.
BUG=chrome-os-partner:7478
TEST=
Change-Id: Icb5cc89836432a11cef80e18eb66bb39a6c9b1d9
BUG=chrome-os-partner:7839
TEST=none
Signed-off-by: Bill Richardson <wfrichar@google.com>
Only tested on BDS at the moment, because that's all I have.
Change-Id: I30c7202856a272953bf7170c6786999378984329
Now that we can jump directly to other images, we don't need this.
We jump to image A by default, unless the recovery button or signal is asserted.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8562
TEST=manual
Reboot -> runs image A
Reboot with reload (F3) held down -> runs RO
Reboot with 'dut-control goog_rec_mode:on' -> runs RO
Change-Id: I8259fe0d738ce0ca897d2f4427d8cf61858b8901
The final piece links the keyboard press and x86_power module.
BUG=chrome-os-partner:8523
TEST=on the link board.
wait for 15 minutes to make host suspend. touch any key to wake up host.
Change-Id: Ie6ae840ae546731daea48ab457fdc056feb5a685
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
The kernel no longer uses port 80 as a delay mechanism, so we don't
need to detect the no-longer-present spammy writes.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7972
TEST=port80 scroll, then boot the system. see a few repeated bytes,
but not piles of 00 and ff's.
Change-Id: Id14dc43ab4e1b15c6bab99a17c062f295a59e7e6
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
This CL adds battery SMI events. And refactors the charging state
machine by adding share state context for all handlers.
Power events are moved to common handler. Minor clean up on console
output messages.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:7526,7937,8450
TEST=manual:
Watch console message when connecting/disconnecting AC adapter and
battery. Check the state transition.
Change-Id: I42eec4f87a9d49bd193cb9dde9080e3dfccbb77c
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
Modify thermal engine to treat temperature threshold as a 3-degree range
instead of a certain value. This way the fan do not keep turning on and
off, while the temperature floating around the threshold value.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Set threshold to current temperature. The fan turns on and does not
immediately turns off.
Change-Id: Iad1de05a409dbbc573a8ffd0ece0dc7961b20806
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Keyboard reset now triggers a cold reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then do 'x86reset cold' for a cold reset or
'x86reset warm' for a warm reset. Check x86 debug console to see that
coreboot detects the warm (soft) reset.
Change-Id: I00930d9f5df98365277cd5c7f2eb8f135c4e4398
Until we solve the I2C hanging issue, we need a reliable way to read
temperature. Add back LPC temperature read command that actually trigger
a I2C read.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8452,chrome-os-partner:8495
TEST=none
Change-Id: Icddd1fe3c1f09889bca633af19041a8aca582de9
Currently temperature polling task sometimes hangs. Until we solve this
problem, fan should not be turned off according to temperature readings.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8479
TEST=none
Change-Id: I3892c55dd18d3533515d5537b1a877e4fc36d631
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
To handle outp(0x64, 0xfe) instruction from host.
BUG=chrome-os-partner:8464,chrome-os-partner:8397
TEST= build on bds and l*. tested on proto 0.5.
Change-Id: I8cb3a870b2a5c7a711dc911ba44e154813e9f123
Jumping (currently rebooting, see crosbug.com/p/8100) to the RW image should
be done by vboot_init(), not vboot_pre_init().
As currently written, vboot_init() has to come AFTER these function calls:
task_init(); // sets up interrupts so that uart will work
watchdog_init(1100); // in case we fall over somewhere
uart_init(); // we'd REALLY like to see some debugging output
system_init(); // may go away with crosbug.com/p/8100
keyboard_scan_init(); // check for F3 to go to recovery mode
flash_init(); // maybe set RO regions (this should come earlier!)
eeprom_init(); // this is where the try_b flags are kept
BUG=chrome-os-partner:7459
TEST=none
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I0ec3f6bcc26a308bb1005a944990963853b88b60
Make thermal engine trigger SMI on overheating and sensor failure.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8249
TEST=none
Change-Id: I1f8c1d05ae69fae4736c4cc92b060b1813007249
(new method, and x86reset command to call it)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8460
TEST=manual: powerbtn, wait for system to boot, x86reset
Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
Note that this is a big security hole and should be removed after we
complete the EC autoupdate mechanism and vboot code.
To full update EC firmware on proto 1.0, we need a manual way to switch
EC running on RO/RW. This CL implements the LPC command.
BUG=chrome-os-partner:8415
TEST=on proto 0.5.
ectool reboot_ec RW_A # EC boots to RW A
ectool reboot_ec RO # EC boots to RO
Change-Id: Ibf050328bc4e3d2c6d72bfc478d6334f11f0eb46
This CL adds LPC commands to provide the following information:
- Design Capacity (dword)
- Last Full Charge Capacity (dword)
- Design Voltage (dword)
- Design Capacity of Warning (dword)
- Design Capacity of Low (dword)
- Battery Type (ascii)
- Model Number (ascii)
- Serial Number (ascii)
- OEM (usually Vendor) (ascii)
- Battery charge cycle count (dword)
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8181
TEST=none
CQ-DEPEND:Iad4d63c996272568b5a661a6716790ef151b29c5
Change-Id: Iabaf7d9862e15c5b21cf5170cf43450e472b7836
Also prints the current timer value when inits are done, and when the
watchdog task first gets to run (after all higher priority tasks sleep
at least once).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I342f86ad087fd18ab064a10a5bcdd0b69ee373d0
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8321
TEST=manual:
type 'battery' in EC serial console, check following fields:
Manufacturer
Device name
Device chemistry
CQ-DEPEND:I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Change-Id: Iad4d63c996272568b5a661a6716790ef151b29c5
Useful when debugging to determine if a user has an official build or
not, particularly early in the devel process where we're handing
builds to everyone. Particularly useful for proto1, since not all
those systems will be case-open servo-attached.
Also move get-version LPC command into system.c, where it's closer to
the system functions it calls (matches what we do for other host
commands).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Idb0f6edf31ca00e32f083be0b0d3f23ab79c5fba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
...since x86_power_in_S0() is a terrible function to have implemented
for gaia chipsets, and I need to add more detectable states for lid
switch handling anyway.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I0c90c6875b27d1bf23f093e88e34eabf2a8c86e4
