The chromeos-cr50 ebuild does not install dev images any more, and
chromeos-cr50-scripts do not try updating dev versions of H1 any more.
Let's stop releasing dev Cr50 images.
BRANCH=Cr50
BUG=none
TEST=tried creating a release image in the release branch, got a
tarball of the desired contents:
$ tar tf cr50.r0.0.10.w0.0.22_ZZAF_ffffffff_00007f80.tbz2
cr50.r0.0.10.w0.0.22_ZZAF_ffffffff_00007f80/
cr50.r0.0.10.w0.0.22_ZZAF_ffffffff_00007f80/cr50.bin.prod
Change-Id: Ib2acaf5f31f7067a98c35c0ec83e730736398a7d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/624193
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Instead of always enabling power to base whenever it is connected,
enable/disable power to base depending upon chipset startup/shutdown.
BUG=b:64460667
BRANCH=None
TEST=Verified following:
1. On system startup, base is connected only after chipset startup.
2. On apshutdown, base is disconnected after chipset shutdown.
3. Wake from base still works.
4. Base still works on firmware screen.
Change-Id: I39454701889650964b7c678b275c984772ecd3e7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/625244
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If current status is the same as requested state, then return early
from base_detect_change without taking any action.
BUG=b:64460667
BRANCH=None
TEST=make -j buildall
Change-Id: I3c403739a2e5c43f31fe77b5633927cf49b974eb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/625243
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The Coral schematics are being changed to reflect that volume up is
connected to GPIO83 and volume down to GPIO82. The current EC code
implemented this same assignment, but introduced an intermediate
signal name to match with previous schematics which had the opposite
assignment. With the signal names fixed on the schematic, the
intermediate #defines are no longer needed.
BUG=b:64012307
BRANCH=None
TEST=manual testing on Coral proto. Verified that up button presses
cause the volume bar to go up and volume down button presses cause the
volume bar to go down.
Change-Id: Ib04f8416e8f36271972fc650bf1593a4babaeb82
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/625063
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Get stack analyzer supported to read annotation file and do basic
annotation on the callgraph.
The basic annotation includes:
1. Add missing calls to the callgraph
2. Ignore functions on the callgraph
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \
--objdump=arm-none-eabi-objdump \
--addr2line=arm-none-eabi-addr2line \
--export_taskinfo=./build/elm/util/export_taskinfo.so \
--section=RW \
--annotation=./extra/stack_analyzer/example_annotation.yaml \
./build/elm/RW/ec.RW.elf
make BOARD=elm SECTION=RW \
ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \
analyzestack
Change-Id: I4cc7c34f422655708a7312db3f6b4416e1af917f
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/614825
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In eSPI systems, when the host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction. The bypass for this
symptom is to set CSAE bit to 1 during initialization and remove the
toggling of CSAE bit from other EC firmware code.
But keeping the CSAE bit at 1 forever also impacts the eSPI performance
a lots. When the core clock is stalled by sleep, deep sleep or wfi
instruction, the eSPI Peripheral Channel transaction is stalled if this
bit is set. The bypass for this symptom is to wake up the core by eSPI
peripheral channel transaction and let eSPI module handle the remaining
packet.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs. Use following script "count=0; while :; do echo "---
iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5;
count=$((${count}+1)); done" to test eSPI performances over 1000
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/620301
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add Parade PS8743 USB Type-C Redriving Switch for USB Host /
DisplayPort.
BUG=b:64598680
BRANCH=glkrvp
TEST=On glkrvp,
Connect Apple dongle and verify mux setting with i2c read.
1. i2cxfer r 1 0x20 0 -> 0x50 (DP/USB enabled)
2. flip i2cxfer r 1 0x20 0 -> 0x54 (Flip bit enabled)
Connect pluggable and verify the same.
Similar testing was successful on second type-c port.
Change-Id: I96ec380024eb659e071b019dd58b3c640fa1cc03
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/616075
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
New released images need higher version number.
BRANCH=none
BUG=none
TEST=built and ran an image, verified version number to be right.
Change-Id: I0b5b690d84b2f281752ad01b154efdebeba2e136
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/621296
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
SVr4/4.3BSD/C89/C99 use a return value of size_t. To
make interaction with code running on both userland
and on the EC easier, change our function prototype
to return size_t as well.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=none
TEST=make buildall -j works
Change-Id: I0f097c4d0db4232d888e1d54e6c1d22f4859a112
Reviewed-on: https://chromium-review.googlesource.com/618269
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Currently, we only use the AC detect interrupt for battery cutoff
support on detachable devices, and we use the RDD detect interrupt for
waking Cr50 from deep sleep. However, Eve accidentally detects RDD
when the EC is off, so this is not a reliable signal - particularly if
Cr50 is explicitly driving EC reset.
Enable the AC detect interrupt all the time, and defer sleep for 5
seconds when it transitions. This will have a negligible effect on
overall power (since AC is not normally transitioning) and will allow
the RDD detect code to be simplified.
BUG=b:64799106
BRANCH=cr50
TEST=manually pull DIOR5 up and down; see AC interrupt debug output.
idle d, wait for sleep, then wiggle DIOR5 and see that cr50 wakes.
Change-Id: I7551f25e27a79573bf4527d8c38994634df621ec
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/619319
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
On max17055, current/temperature register values are in 2's
complement format.
Therefore we need to consider the case of negative values before
doing bitwise operation.
BUG=b:63870414
BRANCH=none
TEST=run 'battery' command and confirm the reported discharge
current looks reasonable.
Change-Id: Iea0c554aecf2b410fc27b547e01ee7a583a0dd00
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/617654
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
A common failure condition on the i2c bus is when the master
unexpectedly stops clocking the bus while the slave is driving the SDA
line low. In this case the master is not able to issue Stop or Start
sequences, which makes the bus unusable.
Good slave controllers are able to detect this condition and recover
from it by removing the pull down from the SDA line. This patch adds
this capability to the g chip i2c slave controller.
A new timer function is created which samples the SDA line twice a
second. If it detects that SDA is low in two consecutive invocations
and the number of i2cs read interrupts has not advanced, it decides
that the "hosed slave" condition is happening and reinitializes the
i2c driver, which removes the hold from the SDA line.
Even though the state of the SDA line is supposed to be accessible
through the I2CS_READVAL register, it in fact is not, reads always
return zero in the SDA bit. To work around this a GPIO (port 0, bit
14) is being allocated to allow to monitor the state of the line, it
is multiplexed to the same pin the SDA line uses.
When the AP is in low power modes the SDA line is held low, this state
should not trigger i2c reinitializations.
CQ-DEPEND=CL:616300
BRANCH=none
BUG=b:35648537
TEST=connected H1 on the test board to an I2c master capable of
stopping clocking mid byte. Observed that the existing code would
just sit in the "hosed" state indefinitely. The code with the fix
recovers from the condition (drives the SDA line high) 500ms to
1s after the failure condition is created.
Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/614391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add a delay to allow the clocks and usb signals to settle.
BUG=b:63767046,b:63867566
BRANCH=cr50
TEST=put the eve ec into hibernate, wait until cr50 enters deep sleep,
use the uart to wake it up, and verify that it eventually reenters deep
sleep
Change-Id: I26463ce3e00996368a791a245b0f9de01737478c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/598448
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When booting scarlet rev1, the initialization of rt9466
is not finished because CHIP REV < 0x05.
Actually, we shouldn't keep the latest CHIP REV in rt946x.h
because it's hard to maintain. And we should try to finish
rt946x_init() no matter what CHIP REV it is.
Also, let's clean up the logging message in rt946x_init()
a bit to make it clear that it's from RT946X.
BUG=chromium:736821, b:63739819
BRANCH=none
TEST=boot scarlet rev1 and confirm the
initialization of rt946x is finished
Change-Id: Ic0b1f837b801cc18744a1222794a055dfe8aa54c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/612585
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In npcx7, we introduce an enhanced version of Serial Host Interface
(SHI) module. This CL adds the support for it.
It includes:
1. Increase the size of IBF/OBF from 64 bytes to 128 bytes.
2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which
level the IBF pointer reaches to trigger an interrupt to core.
The current setting of these two register fields are:
IBFLVL - 64 (half full)
IBFLVL2 - 8 (the size of host command protocol V3 header)
3. Dedicated CS high/low interrupts.
In old SHI module, the way to generate CS high interrupt event is via
EOR bit. However, it has a defect that EOR won't be set to 1 when CS
is de-asserted if there is no SHI CLK generated. It makes the
handling of glitch condition more complicated.
In the new SHI module, we introduce the CS high/low interrupts
(by enabling the CSnFEN/CSnREEN) to make it easier to handle the
glitch.
The new SHI module is enabled during SHI initialization when the chip
family is npcx7.
BRANCH=none
BUG=none
TEST=No build errors for "make buildall". Test host command
communication is ok between npcx7 EVB and a host emulator.
Make sure the glitch condition can be detected and handled.
Also test the driver on gru, make sure it won't break the operation of
old SHI module.
Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/607812
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We previously disabled the USB PHY to the AP. But the BOARD_AP_USB
property lingered on. Remove the property.
Also clean up the idle task deciding when to do utmi wakes. With the
AP USB connection disabled, that's only necessary when the debug cable
is attached, so we can check that explicitly.
BUG=none
BRANCH=cr50
TEST=make buildall; boot CR50_DEV=1 image
Change-Id: If81a7bcfe845d9d70dcc7e16239244a4f5f2427b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616301
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
A subsequent CL will massively refactor the device state machines.
Add the helper functions which will be used by that CL, so that
the refactoring touches fewer files.
No change in functionality.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50 with a CR50_DEV=1 image
Change-Id: I3499d45e93fa15b6de9c04ce398d1c5bfbbc01e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616300
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This reverts commit ddbfe690e2.
Reason for revert: Causes move cursor movements to be choppy, and device
to be very unresponsive during flashrom EC operations.
Original change's description:
> npcx: workaround the bug that SHM data read via eSPI may be corrupted
>
> In eSPI systems, when the Host performs a data read from the Shared
> Memory space, the returned data may be corrupted. This is a result of
> the Core-to-Host access enable bit being toggled (by toggling CSAE bit
> in SIBCTRL register) during an eSPI transaction.
>
> The workaround in this CL is to set CSAE bit to 1 during initialization
> and remove the toggling of CSAE bit from other EC firmware code.
> (i.e., let the CSAE bit be always 1.)
>
> BRANCH=none
> BUG=none
> TEST=No build errors for make buildall. Flash poppy ec image, make sure
> it can boot to OS. Run "ectool version" over 100000 times, no error
> occurs.
>
> Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
> Signed-off-by: CHLin <CHLIN56@nuvoton.com>
> Reviewed-on: https://chromium-review.googlesource.com/590396
> Commit-Ready: Shawn N <shawnn@chromium.org>
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=b:64730183
TEST=flashrom -p ec -r ecr.bin, device still responsive.
Change-Id: Idaeef2707df990b2441a77a15807698d41018449
Reviewed-on: https://chromium-review.googlesource.com/618366
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Printing dots each time device wakes up from sleep causes the terminal
to be overflown with dots, especially in cases when interrupts are
generated at high rate.
Let's replace printing dots with a rotating wheel, the screen is not
going to be wiped out, and one still can tell the rate the wake
interrupts are coming at.
Also, each time the wake source changes, print its hex value.
BRANCH=none
BUG=none
TEST=verified proper printing of the spinning wheel and wake interrupt
sources.
Change-Id: Ic32466234f91b4a19b6186f74296dc6dd765a8fa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/611962
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
the ps8xxx family of TCPCs (ps8751, ps8805) have historically used the
generic tcpci_tcpm_drv functions, but we need to override some of
these entry points because the parade parts need to be woken up before
accessing registers.
in most cases, this doesn't matter because we access the chip in quick
succession where we can "safely" assume the chip is awake -- and the
code is structured to implicitly keep the chip awake. the new case we
need to address here is where we need to suspend the pd_task and TCPC
at an arbitrary point in time. the driver's .release method is called
to shut down the chip, and that involves first waking up the chip to
be able to access its regs to mask off interrupts, etc.
BUG=b:35586896
BRANCH=none
TEST=tested from depthcharge - we no longer get errors in the EC
console logs about TCPC "release" failed.
Change-Id: Ic2a90b71050b3f68c697b1cef48d736ed88b3f41
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616460
Reviewed-by: Shawn N <shawnn@chromium.org>
On Goobuntu, the uapi copy of spidev.h doesnot contain
SPI_IOC_WR_MODE32, however the kernel supports the IOCTL.
To be able to build the tool outside of the ChromeOS chroot,
define it if it's not available.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
TEST=make buildall -j outside of the chroot
BUG=b:35567067
Change-Id: I04ec968e221c7d43f1bdb364a195d371370ec886
Reviewed-on: https://chromium-review.googlesource.com/614645
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Similarly to what we have done with keyboard events, we put touch
events in a FIFO. The AP will need to interpret the timestamp
in the events to be able to process the events correctly tough.
Resume should typically take about 50ms, so a 8-event long FIFO
should be good enough. Also, we bypass the FIFO altogether in most
cases, when the USB interface is not suspended.
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Look at evtest output.
Wait a second, make a swipe, see that events are received in
a very short amount of time after resume (every EP interval/2ms),
but the event timestamps show that some of them are older.
Change-Id: If6ab56396f7d564b19e6c3c528847196ffa4d849
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612221
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We use the unofficial, Windows 8, Relative Scan time HID usage
(Digitizer page, 0x56) to add timestamps to our HID touchpad
events.
The timestamps is a rolling, unsigned, 16-bit integer, with a
resolution of 100us (so it wraps around every 6.5s).
The host will be able to synchronize to that timestamp, resetting
an offset every time the touchpad is quiet a certain amount of
time (e.g. 1 second).
BRANCH=none
BUG=b:63685117
TEST=Flash hammer, timestamps are reported in HID descriptor.
Change-Id: Ie5d56a9df14e464d2cdcd559f550d6e3cc81961f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/603041
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Put key events in a FIFO. This is especially useful when USB is
suspended, so that we can replay the events on resume. This makes
sure that no key strokes are lost on resume from USB autosuspend.
We coallesce events happening within some interval (18 ms), greater
than EP interval (16 ms) to ensure we cannot have a backlog of keys.
The interval must also be short enough to ensure that the intended
order of key presses is passed to AP, and that we do not coallesce
press and release events (which would result in lost keys).
We also discard key events in the FIFO buffer that are older than
1 second. Note that we do not fully drop them, we still update
the report, but we do not send the events individually anymore
(so an old key press and release will be dropped altogether, but
a single press/release will still be reported correctly).
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Wait a second, type something quickly, verify that no keys are lost.
Change-Id: I64d33c15a39ae33af42039fba62cf4ed3abef462
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471188
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
As suggested in CL:411741, makes the follow-up CL that buffers
key strokes much simpler.
We can revisit later if we can still sneak it that change, but,
all in all, we can guarantee the same key latency by halving the
USB endpoint interval.
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, keyboard works.
Change-Id: I6624fde9bd5561ddceb7ce195470d7af7cca7140
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471187
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some USB interface handlers need to know when USB has been
successfully resumed after a wake event. For example, this is
useful so that HID keyboard can send the events at the right time.
BRANCH=none
BUG=b:35775048
TEST=Using USB HID keyboard patches to queue keys in a FIFO:
After USB autosuspends, press a single key and hold it. Without
this patch the endpoint data only gets reloaded on the _next_
event.
TEST=On hammer, I2C passthrough still works.
Change-Id: I9b52b9de16767c8a66c702a5ae70369334a3d590
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/569547
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The command "hostcmd" in console isn't very useful and will cause
stack overflow in console task when processing some hash commands.
BUG=chromium:755048
BRANCH=none
TEST=make BOARD=elm -j
make BOARD=elm tests
There should be no hostcmd command in the console of elm.
Change-Id: Ifa721a1731bc1ebfb39e12430b6631338bdccd9f
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616600
Reviewed-by: Rong Chang <rongchang@chromium.org>
Handle the case of comparing with different kinds of objects.
BUG=none
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
Change-Id: I01056cd39e14d75442d4029b6c64d9843c49cf2a
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616367
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This way, when HOOK_CCD_CHANGE triggers, the debug message is printed
before any of the effects of the change due to other hooks.
No effect on the rest of the code.
BUG=none
BRANCH=cr50
TEST=manual in CR50_DEV=1 image
ccdlock
ccdoops
"CCD change hook called" should be seen before "Enabling I2C" or
"Disabling I2C" messages.
Change-Id: I2e083b70fe8ac3938abc56e14b5e50fe9e237752
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616179
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
When servo_v4 acts as a debug test system (DTS) its expected use
case is for triggering CCD mode and Faft testing. To that end, its
desired default data role is to be a UFP so that the enet and USB
port are accessible by the DUT. However, when servo is acting a
regular SRC port, it makes more sense for the data role pairing to
be consistent with a normal SRC port device which is SRC/DFP.
BUG=b:64720447
BRANCH=servo
TEST=Tested with Eve using twinkie USB PD analyzer. Verified that when
DTS mode is enabled a data role swap request is sent to the DUT and
when DTS mode is disabled that servo_v4 does not send a data role swap
request.
Change-Id: I071f85fc99f1c877d86ef48ec7fa38d6850d5679
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/615813
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
To enable console with DMA, we need to specifically
remap DMA channels for USART1.
ch2/3 and ch6/7 are already used by SPI1/2 modules.
So we have to remap USART1_TX to ch4 and USART1_RX to ch5.
BUG=b:64575809
BRANCH=none
TEST=confirm ec console works on scarlet rev1
Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611147
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Indentation is growing out of control, let's move to a separate
function so that we can return early.
BRANCH=none
BUG=b:35775048
TEST=Flash hammer, usb_wake works.
Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612922
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a shared library to export task information.
Modified the stack analyzer to get information from the shared library.
Show allocated stack sizes of tasks in the stack analyzer.
To get the all task information (including the allocated stack size),
A shared library is added and compiled with the board to export all
configurations of the tasklist.
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \
--objdump=arm-none-eabi-objdump \
--addr2line=arm-none-eabi-addr2line \
--export_taskinfo=./build/elm/util/export_taskinfo.so \
--section=RW \
./build/elm/RW/ec.RW.elf
make BOARD=${BOARD} SECTION=${SECTION} analyzestack
Change-Id: I72f01424142bb0a99c6776a55735557308e2cab6
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611693
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The center supply is fixed to .9V on nefario, it had not the
enable pin for controlling.
Also the Nefario unused the led for battery.
BUG=b:63408169
BRANCH=none
TEST=Tested on nefario, check the gpioget
Change-Id: I339ce2cb2fb530cec393a352d920ea21fd8a8464
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/612969
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Add a static analysis tool for firmware stack usage.
Add an new Makefile rule to analyze the stack usages of firmwares.
Details about the tool can be found in extra/stack_analyzer/README.md.
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm && make BOARD=elm build/elm/RW/ec.RW.taskinfo && \
extra/stack_analyzer/stack_analyzer.py \
--objdump=arm-none-eabi-objdump \
--addr2line=arm-none-eabi-addr2line \
./build/elm/RW/ec.RW.elf ./build/elm/RW/ec.RW.taskinfo
make BOARD=${BOARD} SECTION=${SECTION} analyzestack
Change-Id: Ifb1b5f5ad6be8f8b125b14d6ee03e25cb385895b
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/576411
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
