Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8350
TEST=manual
Hack a task function to return. Then see that it prints an error to
the debug console and the EC continues running, instead of seeing a
hard-fault.
Change-Id: Iacd2b83c4d4845bb8e6c61e07c3150df8edc7e49
Add build information (date/time/builder) which can be displayed at the
EC console.
Generate a version from the board name and the branch tag.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:27013
TEST=on BDS, run version command on the console.
inspect the built binary.
Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
The temperature calculation currently uses fixed point operations.
Change it to use floating point for better readability and maintenance.
Also changes disable_fpu() to accept parameter which serves as
optimization barrier to prevent floating point operations after
disabling FPU.
BUG=chrome-os-partner:7801
TEST=In console, tempremote "tempremote 29715 -105000 6390" gives 28506.
Change-Id: Ib766904b8feb9a78eac9f7cd53afeca85091c5a5
Signed-off-by: Vic Yang <victoryang@chromium.org>
Add an arch include folder. Implement sqrtf for Cortex-M in math.h.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: Ib7b480b6a0bf7760f014a1f73df54673a9016cb6
Signed-off-by: Vic Yang <victoryang@chromium.org>
Implement enable_fpu() and disable_fpu().
enable_fpu() disables interrupt and then enables FPU.
disable_fpu() disables FPU and enables interrupt.
Also added a CONFIG_FPU flag.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521
Signed-off-by: Vic Yang <victoryang@chromium.org>
Preparatory work to introduce a second SoC : 2nd series 2/4
Avoid introducing platform specific dependencies in common files where
they are not necessary.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS and Link
Change-Id: If2ccd022e4956425222b55a5a48ca7522857e7f0
Preparatory work to introduce a second SoC : 2nd series 1/4
The atomic operations are SoC independant since they are only using
LDREX/STREX instructions which are just core specific ARMv7-M).
The watchdog header defines the API which is common to all platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Preparatory work to introduce a second SoC : 5/5
All Cortex-M3/4 have the same NVIC registers at the same address.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
Preparatory work to introduce a second SoC : 4/5
Allow to use the common code for most SoC.
Also simplify the UART code, we don't need speed on the panic path.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=trigger a panic and check the UART output on BDS
Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
Preparatory work to introduce a second SoC : 3/5
We split the drivers files which contain SoC specific drivers from the
OS files which only depend the actual CPU core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and test a few commands on the console.
Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
