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NVIC registers are not SoC specific

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Preparatory work to introduce a second SoC : 5/5

All Cortex-M3/4 have the same NVIC registers at the same address.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=run EC firmware on BDS and check a few console commands

Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
This commit is contained in:
Vincent Palatin
2012-01-25 22:42:11 +00:00
parent 9301cef981
commit 9a465855f8
4 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
chip/lm4/registers.h
View File

@@ -183,12 +183,6 @@ static inline int lm4_fan_addr(int ch, int offset)
#define LM4_DMA_DMACHMAP2 LM4REG(0x400ff518)
#define LM4_DMA_DMACHMAP3 LM4REG(0x400ff51c)
#define LM4_NVIC_EN(x) LM4REG(0xe000e100 + 4 * (x))
#define LM4_NVIC_DIS(x) LM4REG(0xe000e180 + 4 * (x))
#define LM4_NVIC_PRI(x) LM4REG(0xe000e400 + 4 * (x))
#define LM4_NVIC_APINT LM4REG(0xe000ed0c)
#define LM4_NVIC_SWTRIG LM4REG(0xe000ef00)
/* IRQ numbers */
#define LM4_IRQ_GPIOA 0
#define LM4_IRQ_GPIOB 1

3
chip/lm4/system.c
View File

@@ -6,6 +6,7 @@
/* System module for Chrome EC */
#include "console.h"
#include "cpu.h"
#include "registers.h"
#include "system.h"
#include "uart.h"
@@ -234,7 +235,7 @@ int system_reset(int is_cold)
{
/* TODO: (crosbug.com/p/7470) support cold boot; this is a
warm boot. */
LM4_NVIC_APINT = 0x05fa0004;
CPU_NVIC_APINT = 0x05fa0004;
/* Spin and wait for reboot; should never return */
/* TODO: (crosbug.com/p/7471) should disable task swaps while

23
core/cortex-m/cpu.h Normal file
View File

@@ -0,0 +1,23 @@
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Registers map and defintions for Cortex-MLM4x processor
*/
#ifndef __CPU_H
#define __CPU_H
#include <stdint.h>
/* Macro to access 32-bit registers */
#define CPUREG(addr) (*(volatile uint32_t*)(addr))
/* Nested Vectored Interrupt Controller */
#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
#endif /* __CPU_H */

12
core/cortex-m/task.c
View File

@@ -10,10 +10,10 @@
#include "config.h"
#include "atomic.h"
#include "console.h"
#include "cpu.h"
#include "task.h"
#include "timer.h"
#include "uart.h"
#include "registers.h"
#include "util.h"
/**
@@ -253,19 +253,19 @@ uint32_t task_wait_msg(int timeout_us)
void task_enable_irq(int irq)
{
LM4_NVIC_EN(irq / 32) = 1 << (irq % 32);
CPU_NVIC_EN(irq / 32) = 1 << (irq % 32);
}
void task_disable_irq(int irq)
{
LM4_NVIC_DIS(irq / 32) = 1 << (irq % 32);
CPU_NVIC_DIS(irq / 32) = 1 << (irq % 32);
}
void task_trigger_irq(int irq)
{
LM4_NVIC_SWTRIG = irq;
CPU_NVIC_SWTRIG = irq;
}
@@ -285,8 +285,8 @@ static void __nvic_init_irqs(void)
uint8_t irq = __irqprio[i].irq;
uint8_t prio = __irqprio[i].priority;
uint32_t prio_shift = irq % 4 * 8 + 5;
LM4_NVIC_PRI(irq / 4) =
(LM4_NVIC_PRI(irq / 4) &
CPU_NVIC_PRI(irq / 4) =
(CPU_NVIC_PRI(irq / 4) &
~(0x7 << prio_shift)) |
(prio << prio_shift);
}