Prevent spurious wake when servo is not connected.
BRANCH=none
BUG=b:36119938
TEST=Measure pull up value with a multimeter when servo is not
connected: value around 30k when host in S0 and S3.
Change-Id: I8bd54e4dcfd5c65f1f0cd32ffd4a70cedb979cc2
Reviewed-on: https://chromium-review.googlesource.com/452652
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:35775100
BRANCH=None
TEST=Verified that tablet mode switch events can be seen in evtest.
Event: time 1489093184.754803, -------------- SYN_REPORT ------------
Event: time 1489093196.842930, type 5 (EV_SW), code 1 (SW_TABLET_MODE), value 0
Event: time 1489093196.842930, -------------- SYN_REPORT ------------
Event: time 1489093198.839809, type 5 (EV_SW), code 1 (SW_TABLET_MODE), value 1
Event: time 1489093198.839809, -------------- SYN_REPORT ------------
Change-Id: Id47e817ba12294cc07281df3e04a9d68dec40ee7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451582
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Send EC_HOST_EVENT_MODE_CHANGE upon base attach and detach, to
wake the AP as required. Also, re-factor the code for base detect
status change to allow single function for all actions that need to be
taken on base attach/detach.
BRANCH=none
BUG=b:35775085
TEST=Flash poppy, powerd_dbus_suspend, EC wakes the AP on base
attach. Confirmed in eventlog that wake event is seen by AP:
53 | 2017-03-08 16:44:58 | ACPI Enter | S3
54 | 2017-03-08 16:45:06 | ACPI Wake | S3
55 | 2017-03-08 16:45:06 | EC Event | Mode change
Change-Id: I5b488b32df0454f14a9d784e7564be7e999caadd
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448379
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SPI initialization interrupt needs to be generated only when there
was actual data received while CS was asserted and after transaction
finished (i.e. CS is de-asserted).
BRANCH=cr50
BUG=b:35774896
TEST=verified on a bob with updated AP firmware
Change-Id: Ifc4b11870d511d47e9607a2001d845ee1e153f7f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452792
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
To improve robustness of booting under low battery condidtions,
increased the thershold CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC from 1 to
2. The effect of this change is that try srouce mode will be disabled
until the battery has >= 2% of charge. This prevents the port from
disconnecting, when a USB PD charge is connected under this low
battery condition.
BUG=b:36093023
BRANCH=None
TEST=Verfied that when the battery charge was < 2% the USB PD state
machine on Eve did not go to state 15 (SRC_DISCONNECTED) after
initially attaching as a sink device. When the battery charge is >= 2%
then observed that the transition to state 15 happens.
Change-Id: I50123bc4f98e7a8dc793d9a9844d1d9961fde121
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452739
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Follow reef setting.
When battery is fully charged, pyro starts discharging to protect
battery and starts charging again when charge level goes down
around 95%. To prevent the battery LED from showing green with the
charger plugged in.
BUG=none
BRANCH=reef
TEST=Fully charge Electro. Plug in OEM charger. LED lights green.
Change-Id: If8560cbc3975b35ae84a9df2bdf5331c653143d1
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/449600
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This command is handy in debug images when rollback protection needs
to be reset.
Manufacturing data stored in the last quarter of the INFO1 space is
preserved across the erase session.
BRANCH=cr50
BUG=b:35774863
TEST=built a non-debug image with the first map location in the
manifest set to zero, booted the new image. Then built and booted
a debug image with this patch included. Using sysinfo command
verified that the info map has one location zeroed, then ran
eraseflashinfo command and checked sysinfo output again. The info
map shows no more zeroed locations, and tpm still reports statues
as "manufacutred"
Change-Id: I58e2a6f6371b6ce656c1d6cc373dfdc6f9d9f5be
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450906
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
With enabling INFO1 map based rollback protection it is important to
be able to tell the state of the flash map and the currently installed
images' infomap header field.
The new function counts number of zero words in the info map and zero
bits in both RW headers, and returns them in a string printed out by
the sysinfo command.
BRANCH=cr50
BUG=b:35774863
TEST=built images with different manifest info field contents and
verified that the string printed by the sysinfo command makes sense.
Change-Id: If633a6c678dc34197b2dad116b6180b2d549e089
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450905
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Debug images should run on any H1 device, no matter what its INFO mask
is set to. This is achieved by emptying the info {} section of the
manifest when building images with nonempty CR50_DEV in the
environment.
BRANCH=cr50
BUG=b:35774863
TEST=built images with and without CR50_DEV=1, verified that the
manifest has the info{} section emptied when CR50_DEV is set.
Verified that the RW images boot fine.
Change-Id: Ied314c175d5c02f4108b7af85c244b6da8547616
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450904
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The cr50 RO image compares INFO rollback map space against the
contents of the RW image's infomap field.
To ensure that no rollback is possible, the RW should verify that the
INFO space state is consistent with the current RW and RW_B headers,
and if not, update the INFO state to comply.
This should happen only when running prod images, so that debug images
could be rolled back if so desired.
Also fixed the bug in functions enabling read and write access to the
INFO1 region. Write access is now a superset of read access setting.
BRANCH=cr50
BUG=b:35774863
TEST=as follows:
- built and ran a new image, observed it start successfully;
- modified the manifest to erase the first map location, built and
ran a new image, observed it start successfully
- restored the manifest, built and tried running a new image,
observed that the earlier version is starting.
Change-Id: I62253c3e98cd24ed24424b8bb9de22692a262d89
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447966
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
In order to prevent noise when using the system with a full
battery the EC can disable charging at full until it reaches
97% and then turn on charging again.
However this needs additional LED handling to ensure that the
charging LED is shown green in this state.
BUG=b:36024657
BRANCH=none
TEST=manual test with full battery on Eve P1b, ensure that the
LED is still green when battery is full and discharging.
Change-Id: Iad2b1462ad85163dc9702ff1154f3ff10eb0f7ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450953
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Limit max input current to 95% for safety.
(changes ported from reef)
BUG=b:36024657
BRANCH=none
TEST=manual testing on Eve P1b board
Change-Id: I6beb3fc4ac62e40bb7c8dfc8463e6a0d177997d9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450952
Reviewed-by: Scott Collyer <scollyer@chromium.org>
To prevent in rush current from the charger when attached, enable
discharge on AC until the charger is detected.
This required enabling charger profile override which was previously
not getting called, so discharging was never disabled.
BUG=b:36024657
BRANCH=none
TEST=build and boot on eve, ensure battery charges with AC attached
Change-Id: Ie5912c1d4981d894366f36f31607d5f66a04c346
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450951
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Limit battery charge voltage to prevent battery over-charge due to
regulation inaccuracy.
(ported from reef board)
BUG=b:36024657
BRANCH=none
TEST=build and boot on reef and ensure charging is still functional
Change-Id: I90dd8bda3d67a6c50aa39bbd096239565c73b7c5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450950
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Allow the board to override the hardcoded 97% value for reporting to
the host (and controlling LED behavior) when the battery is "near full".
When enabling "discharge on ac" with a full battery the battery stops
taking a charge until it reaches ~94% SOC (the actual value is not set
but rather comes from a smart battery status bit) but the user will see
the device as discharging between 97% and 94%.
The host side view can be worked around with a powerd preference.
The LED behavior is all inside the EC, so you end up with the LED showing
discharging when it should not.
If we allow the board to override this to 94% then the LED and host
behavior is consistent.
BUG=b:36024657
BRANCH=none
TEST=make -j buildall
Change-Id: Ie5ab8e41b87101e201073276bf441e25be7daca4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450949
Reviewed-by: Scott Collyer <scollyer@chromium.org>
To make sure cr50 usb works, we need to disable sleep immediately
after the usb controller detects that usb has resumed. The usb WKUPINT
is asserted on usb resume, but cr50 doesn't currently respond to that.
This change umasks the usb wakeup interrupt, so that USB ISR will
disable sleep on resume.
BUG=b:35774906
BRANCH=none
TEST=Run 100 'usb_updater -f' 100 times sleeping 20 seconds in between
each run. Verify there are no failures and cr50 still goes to sleep
between each run.
Change-Id: I1819deaa3988bcf2a85686d1b9d57092ba264c4d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450900
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Pass "full_build_string" to ccprintf() as expected. I believe that this
code only worked previosly due to blind luck; the compiler allocated
"full_build_string" on the stack in such a way that it was available at the
end of the call frame for ccprintf().
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ib307547a4c4d6300ccf018b33aee4db7a4f364f8
Reviewed-on: https://chromium-review.googlesource.com/451084
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Matches the pressure multiplier used with elan trackpad on Chrome OS
(3.1416). We do fixed point arithmetic to avoid the need for
floating point or non-power of 2 division.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: Ic3daad2645839955734eb7cbd9a60bbdf2520ce8
Reviewed-on: https://chromium-review.googlesource.com/450994
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There were 2 mistakes when setting the data/power roles for automatic
GOOD_CRC:
- the bit numbers for data role and power role were swapped.
- the function can only set and not reset the bits.
Try to simplify this code by:
- removing the duplicated name for register 0x9C (aka AUTO_GOODCRC_1)
- avoiding the multiple read/modify/write by using AUTO_GOODCRC_1 for
the actual settings (and letting the enable bit always on)
and GOOD_CRC_2 for enabling/disabling it, so we can do simple writes.
- answer only on SOP (not SOP' or SOP'').
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=reef
BUG=b:35648282
TEST=On Snappy, connect a given power supply, record the USB PD traces
and see that the GOOD_CRC messages are still correct after the DR_SWAP.
Change-Id: I848b1dcbc0e06806649e64a9664f3fba21bdd448
Reviewed-on: https://chromium-review.googlesource.com/448040
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: S Wang <swang@analogix.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This is required so that the kernel can enable/disable remote wake-up
capabilities, and in particular for the kernel to enable autosuspend.
Also, properly implement GET_STATUS.
BRANCH=none
BUG=b:35579996
TEST=echo auto > /sys/bus/usb/drivers/usb/X-Y/power/control, device
autosuspends after 2 seconds, and wakes on keypress.
Note that this introduces other bugs, where keys are missing,
repeated, see b/35775048.
Change-Id: I7ddd257ac3877d27fb2da813f20583a614a0169b
Reviewed-on: https://chromium-review.googlesource.com/450826
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The issue is with how we have the sys_rst_l wake pin setup. How it is
now, the gpio controller never sees that sys_rst_l is asserted, so it
can't tell when there is a rising edge.
sys_rst_l is a rising edge wake pin. Cr50 would enter sleep with
sys_rst_l high. While cr50 was asleep sys_rst_l would be asserted and
then deasserted. The rising edge would wake cr50 up, and when cr50 woke
up the gpio controller would see that sys_rst_l is still high, so it
wouldn't think there was an edge and it wouldn't trigger the tpm reset
interrupt.
This change makes sys_rst_l wake low instead of wake rising. This means
that cr50 will remain awake whenever sys_rst_l is asserted and it will
be awake to see the rising edge on sys_rst_l.
BUG=b:35774896
BRANCH=cr50
TEST=Turn off bob. Wait until cr50 enters regular sleep. Turn the device
back on and make sure it doesn't boot to recovery.
Change-Id: Ibee6c8112d32b3abb8953aa71d68e1f510932286
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450874
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reef RAM / code regions aren't a power of 2, so we cannot program MPU
to protect the regions we desire.
BUG=b:36037354
BRANCH=none
TEST=Boot to OS
Change-Id: I2d1e87eb97f9524620943262845823331f9f71a0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450831
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit changes the behaviour of handling the CCD_MODE_L pin. When
Cr50 is not in CCD mode, it will stop driving the pin and turn it into
an input. This allows the pin to be driven by the EC. Cr50 will then
poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD
mode. Once the pin is deasserted, CCD mode is disabled.
However, when Cr50 itself makes the decision to enter CCD mode, it
changes the pin from an input to an output and drives the pin low.
NOTE: The rdd interrupt does not directly trigger CCD mode, but now
drives the pin low. A side-effect of the pin going low is that CCD is
enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the
pin to be setup as an input again.
CQ-DEPEND=CL:448988
BUG=b:35804738
BRANCH=cr50
TEST=Flash dev board, use `ccd` console command to both enable and
disable CCD. Verify that when CCD is enabled, the state of DIOM1 does
not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low
enables CCD. Letting it float disables CCD.
TEST=Verify that CCD mode is reflected in the device state.
Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/448161
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is used for passing button information from EC to AP.
BUG=b:3577493
BRANCH=None
TEST=Verified using evtest that kernel is able to see button
press/release information.
Change-Id: Ifcad417c232c4e6e27e1024d2bed27133250fa07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450937
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We had disabled wakeups on the AP phy when we were running on gru,
because the AP phy was not in use. We never changed that for reef, so
UTMI wakeups were disabled even when the AP USB was supposed to be
enabled. After Cr50 went to sleep any usb transactions would drop bits,
because Cr50 wouldn't notice anything was happening until it woke up on
one of the HOOK_TICK events.
This change reenables UTMI wakeups on boards with AP usb. It writes 1 to
USB_PCGCCTL_STOPCLK. This makes the controller disable the PHY clock
whenever it detects a usb suspend. When it resumes out of suspend, this
bit has no effect.
BUG=b:35774906
BRANCH=cr50
TEST=Boot up reef. Wait until cr50 goes to sleep run 'usb_updater -f'
and verify that it runs successfully. Make sure deep sleep still works
Change-Id: I54bd866111b5c9b5738575f23757e0cbe4907ec4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448988
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
pdcontrol suspend command will be used to prevent tcpm from putting
the chip into sleep while firmware update is taking place. Currently
the command suspends or resumes port 0. This patch makes the command
apply to ports individually.
pd enable console command now takes a port number:
pd <port> enable/disable.
This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED.
When it's defined, PD communication is disabled at startup.
Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to
disable PD communication at startup. Therefore, this patch defines
CONFIG_USB_PD_COMM_DISABLED in its board.h.
BUG=b:35586859
BRANCH=none
TEST=From AP console:
localhost # /tmp/ectool pdcontrol suspend 1
[600.188013 TCPC p1 suspended!]
> pd 1 state
Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020
localhost # /tmp/ectool pdcontrol resume 1
[678.516613 TCPC p1 resumed!]
> pd 1 state
Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
From ec console:
> pd 1 disable
Port C1 disable
> pd 1 state
Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
> pd 1 enable
Port C1 enabled
> pd 1 state
Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447968
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There are two types of signing of CR50 images - prod and dev.
Designating images built with CR50_DEV variable set in the environment
as DEV is confusing, as this has nothing to do with the signing type
(dev vs prod), and is in fact indicating an image with many debug
features enabled.
This patch changes the string to "DBG".
BRANCH=cr50
BUG=none
TEST=verified that the modified image has correct string in the
version field:
> vers
Chip: g cr50 B2-D
Board: 0
RO_A: * 0.0.10/29d77172
RO_B: -1.-1.-1/ffffffff
RW_A: 0.0.16/DBG/cr50_v1.1.6137-1624610+
RW_B: * 0.0.16/cr50_v1.1.6137-1624610+
Build: 0.0.16/cr50_v1.1.6137-1624610+
tpm2:v0.0.287-1a68fe6
cryptoc:v0.0.8-6283eee
2017-03-06 16:51:15 vbendeb@eskimo.mtv.corp.google.com
>
Change-Id: I06a97a6aff5418a4d02e71ca23813e6d2005da5c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450903
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This counter will count the number of times the system enters deep
sleep. This is mainly for debugging purposes. With access to the deep
sleep count you can start a s3 suspend stress for hundreds of iterations
and verify that cr50 entered and resumed from deep sleep the right
number of times.
BUG=none
BRANCH=cr50
TEST=Wait until cr50 enters deep sleep. Wake it up and verify the
counter increased. Run 'idle C' and verify it is reset to 0.
Change-Id: Icb70a2fefedd82ea10934093f4c917da16b8d4ea
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448334
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
If we are using more PWRDN or LONG_LIFE scratch registers we want to
make sure we don't clobber any existing uses. The use for each scratch
register is not documented anywhere. This change adds a comment to
init_chip with listing the uses for each long life and pwrdn scratch
register.
BUG=none
BRANCH=cr50
TEST=make buildall
Change-Id: I1e7d5b1f86dfa1a996671e864fe768976987a85e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448819
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Once ec receives LRESET/PLTRST on eSPI mode, both WUI57 of table 0 and
WUI15 of table 2 will be issued at the same time. We don't need two WUI
sources to indicate LRESET/PLTRST event on eSPI mode. This CL removes
initialization of LRESET/PLTRST of WUI57 of table 0 in lpc_init() for eSPI.
BUG=b:35954584
BRANCH=None
TEST=Verified that no more watchdog resets are seen on poppy.
Change-Id: Ib35b574d937c40d417ac707296ec080fd0244cf8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450022
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Using -O3 optimization level rather than -Os results in a large speed-up
for a minor code size increase for the RSA code with our current GCC
toolchain.
Add the CONFIG_RSA_OPTIMIZED option to do it on platforms which are not
too size-constrained.
On cortex-M4 based STM32L432, I'm measuring a 37 to 40% speed increase
(depending on CPU frequency) for a 200 bytes code size delta.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=manual: benchmark RSA2048 with F4 exponent on STM32L432:
-Os -O3
@16Mhz 185163 us --> 111942 us
@80Mhz 39286 us --> 24582 us
Change-Id: I8c2e4b757f037f4f645fb73ba0faaaa471b24896
Reviewed-on: https://chromium-review.googlesource.com/445218
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When battery is fully charged, Reef starts discharging to protect
battery and starts charging again when charge level goes down
around 95%. To prevent the battery LED from showing blue with the
charger plugged in, this patch adds a new state for discharge +
nearly full. Reef shows a color indicating battery is full if
an external charger is present.
BUG=b:35775017
BRANCH=none
TEST=Fully charge Electro. Plug in OEM charger. LED lights blue.
Change-Id: I4c7c62f2c51c1d39188d1b271331984e89d5d7a3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448961
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the interrupts of MIWU group E/F/G/H of table 0 are the same
(interrupt 11), we need to handle LPCs' and GPIOs' events at the
same ISR. But we also found there is a leak that ec has the chance
to skip the other events which don't belong to GPIOs unexpectedly.
(For example, LRESET and eSPI Reset) This CL fixed this issue by
only clearing pending bits belong to GPIOs in their ISRs.
BRANCH=none
BUG=b:35648154
TEST=passed warm-reset testing on pyro over 12 hours.
Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In the process, also manually specify all regions exact size,
which will be useful later on (e.g. when using RO/RW of different
sizes).
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer -j; flashwp true/rb/rw protects the expected
regions, flashwp noall unprotects them.
Change-Id: Ib31d9384060b1373e0834cfecb4ebd0a7bafd356
Reviewed-on: https://chromium-review.googlesource.com/430520
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
