Commit Graph

4 Commits

Author SHA1 Message Date
Kyoung Kim
166d7a72df ISH: Added UART Rx/Tx interrupt mode
Added UART Tx/Rx interrupt mode related code.

BUG=None
BRANCH=None
TEST=On ISH enabled Reef board, check if Tx message is working
and tested Rx input from console with console command.

Change-Id: I5067304dc74abc29bbbea983b22db3e193e36e6b
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/424322
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
2017-01-11 14:46:29 -08:00
li feng
f50b1cec17 ish: correct i2c write operation buffer size
ISH i2c write operation failed due to wrong buffer size passed.

BUG=None
BRANCH=None
TEST=On reef ISH enabled board, verified sensor i2c read/write are
successful.

Change-Id: Icda625ad16e1e60832bb22e3148e23fcb8e6a937
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/418876
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-12 18:34:32 -08:00
Kyoung Kim
fa1cec0b60 ISH: fix UART reference clock
UART reference clock is 100KHz for ISH4 and 120MHz for ISH3

BUG=none
BRANCH=None
TEST=`make buildall -j`

Change-Id: Ie33e0bd33e0a0c8e56a58fcf4a48677d38c9d61e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/409594
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11 00:12:33 -08:00
Jaiber John
d7b938f857 ish: Add support for ISH chip
This patch adds the initial support for ISH chip to enable the EC
firmware to boot on Intel Integrated Sensor Hub (ISH). The following are
enabled:

1. Inter-Processor Communication (IPC) driver that enables the ISH to
communicate with the host Operating system via shared registers.
2. High Precision Event Timer (HPET) driver that provides configurable
timers for the FW to use in task scheduling.
3. I2C bus driver for accessing sensors.
4. UART console driver with TX support only.

BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`

Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336710
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Jaiber J John <jaiber.j.john@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Jaiber J John <jaiber.j.john@intel.com>
Reviewed-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-04 18:31:29 -07:00