Prepare the future and return a WebUSB descriptor to be able to use the
dongle from this website.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=manual: enumerate WebUSB descriptors with lsusb and connect to
a WebUSB page in Chrome R61+.
Change-Id: I6a36538667ac114fc4b40cb87b2d6e946e265c4d
Reviewed-on: https://chromium-review.googlesource.com/677285
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Kionix Accel does not have FIFO, enable force mode for it.
Chrome needs sensor for screen orientation, set to to 10Hz
in S0 in the EC.
BRANCH=none
BUG=b:62029360
TEST=none
Change-Id: I5545580f2073e9d1145bd86cfcd594164119cae7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675575
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
The TCPC interrupts were setup, but they weren't enabled yet. This
commit enables the interrupts.
Additionally, a "tcpcdump" debug command is added. This can be removed
later or expanded upon to be more generic.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that we respond to TCPC alerts.
Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670063
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes LED pulse using deferred call to save RAM and
CPU cycles.
This patch also adds led_alert API. It blinks LED as a warning.
BUG=b:37646390
BRANCH=none
TEST=Verify LED on in S0, pulse in S3, and off in S5.
Run 'led alert' command.
Change-Id: I8c61f91f095eed562d2ee9582868879241df626f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Just setting the global VRMODECTRL register is not enough to disable
the effect of SLP_S0# signal. Each VR control register needs to be set
correctly to ignore the effect as well. However, disabling VR decay on
SLP_S0# assertion by default results in additional power consumption
during S0ix. In order to prevent this, VR decay on SLP_S0# assertion
needs to be enabled and disabled dynamically as follows:
1. By default on EC boot, PMIC will be initialized to disable VR decay
on SLP_S0# assertion.
2. When host indicates intent to enter S0ix, EC will enable decay of
VRs on SLP_S0# assertion.
3. When host exits from S0ix and updates the intent to no longer enter
S0ix using host command, EC will disable decay of VRs on SLP_S0#
assertion.
actual SLP_S0# assertion because PMIC seems to honor the setting only
at SLP_S0# assertion and not if it is already asserted.
BUG=b:65732924
BRANCH=None
TEST=Verified with this change that the failing Lux device is stable
for a long time even with runtime S0ix.
Change-Id: I9c5afb408694b3b467e85dcea723f7574bc639c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get a Twinkie firmware image with the regular Twinkie sniffer
firmware in the RO partition and a firmware behaving as a USB PD sink in
the RW partition, I had created the (questionable) build_rw_variant bash
script.
Now the EC build can do this natively, so remove the script and the
dedicated task list and use conditional task declaration in the
ec.tasklist.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=build the former firmware with './board/twinkie/build_rw_variant',
build the new one with this patch and 'make BOARD=twinkie' -j,
compare the 2 resulting binaries, they are identical.
Change-Id: I3adb24e2c2825e5bd6f43a7440f829efd70038cc
Reviewed-on: https://chromium-review.googlesource.com/677284
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When battery is at critical charge level, reject charge port disable
request. Since battery is not able to provide enough power to the EC
on boot, we should not cut off our input power, regardless of
dual-role determination or other charging policy.
(Reference:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/351224)
BUG=b:64703097
BRANCH=None
TEST=make -j buildall. Verified that both right and left port are
able to boot the EC up successfully. No reboot loops observed in
critical battery conditions.
Change-Id: I098083036388783c0975ac772da3a3412895e26f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675586
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Vbus adc channel was defined as 0 in the enum, however, we don't
actually have a Vbus ADC channel, therefore it should be defined as -1.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that when charge manager tries to read the
Vbus voltage, the EC doesn't panic due to a non-existing channel.
Change-Id: I53dd3259afc7ae76f587e5b7925ce2f9daa06402
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670123
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit enables the PSL pins for zoombini. Previously, we were
initializing the PSL_OUT pin to high, but it actually turns out that
setting the output from a 0 to a 1 indicates that the firmware wants to
remove Vcc1. This caused the EC to not boot up. This commit removes
the improper initialization of the GPIO and additionally sets up the
hibernate wake pins accordingly such that they can be used by the PSL
glue logic.
BUG=b:65647213
BRANCH=None
TEST=Flash zoombini without rework. Verify board comes up okay.
TEST=Enter `hibernate` on console; Verify board goes to sleep. Verify
that each hibernate wake pins wakes up the board successfully.
Change-Id: Ife1b82eec7957b44bbe409cdeba9c3972168812f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670062
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The keyboard config was the old chrome OS keyboard, but it should be the
new one introduced in April of this year.
Additionally, change KSO2 inverted to be push-pull instead of open
drain. This was causing the entire row to not be detected.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that every key on the keyboard is detected.
Change-Id: I408739eed84f06bd9a2df5a9053c75859f8aaa0b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670061
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The LEDs were on when they were intended to be off. This commit just
inverts the duty cycles.
BUG=None
BRANCH=None
TEST=Flash zoombini. Verify all LEDs are off. Plug in battery, verify
that Red LED is on.
Change-Id: I78e2bce45603fd223ebaeacb024a210c5db70123
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670060
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is used for factory test with following command
1. ectool command
ectool led power query
ectool led power green=100
ectool led power red=100
ectool led power amber=100
ectool led power off
ectool led power auto
2. console command
led debug >> enter debug mode
led green
led red
led amber
led off
led debug >> exit debug mode
BUG=b:65651340
BRANCH=master
TEST=`ectool ...` works good
Change-Id: Icb87e479075d90f509d60121a3e1df0afe66d41f
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/666418
This change makes the power LEDs pulse using PWM.
S0: solid green.
S3: pulsing amber (= mix of green and red)
S5: off
BUG=b:64975836
BRANCH=none
TEST=Verify LED behavior described above on Proto3
Change-Id: I696cf8279dd762236b7b7f000a316820d58916bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669773
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some Elan touchpad ICs have a different firmware sizes (48, 56, or 64
KB). We use CONFIG_TOUCHPAD_VIRTUAL_SIZE, set in the board file, to
determine the appropriate size, and, at runtime, we sanity check the
firmware size according to the IC type reported by the touchpad.
BRANCH=none
BUG=b:65188846
TEST=Manually modify the CONFIG_TOUCHPAD_VIRTUAL_SIZE in hammer,
executed and verified both (1) "EC_ERROR_UNKNOWN" returned
(2) ic_type shows 0x09 on EC console
TEST=Successfully flashing 48k firmware using CL:658920 on hammer and
56k firmware on staff. With success here, we specifically test
with different firmware version and make sure it reflected in
hammerd's touchpad info.
Change-Id: Ib30917d8376d4a2e8b6137daabad2341ac48d1f8
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/664937
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Proto2 board has the line ADP_IN, which is raised to 2.5 V when a BJ
adapter is plugged. This patch makes EC running on proto2 and above
use this line to detect the power source at boot (as opposed to proto1
guessing a BJ adapter is plugged if PPVAR_BOOSTIN_SENSE is 19v).
BUG=b:37573548
BRANCH=none
TEST=Boot proto3 Fizz on BJ and Type-C.
Change-Id: I4052a73729d62694ce154bfb33255974dc110841
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/626879
Servo / Suzy-Q related debugging methods is a big challenge
in factory especially after servo debug header is removed.
Expose some information to OS from EC will do a great help
for massive production.
+ expose charge/battery related state to ectool
1. chg_ctl_mode
2. manual_mode
3. battery_seems_to_be_dead
4. battery_seems_to_be_disconnected
5. battery_was_removed
6. disch_on_ac (learn mode state)
7. battery DFET
BUG=b:65265543
BRANCH=master
TEST=`ectool chargestate param x10000~0x20006 get correct state`
Change-Id: Ib64ab3c7b68a634ea098425c93e5234361cd1936
Reviewed-on: https://chromium-review.googlesource.com/662318
Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch gives the highest priority to dedicated chargers. It
means if a dedicated power supply is being connected, other power
supplies such as USB-C adapters will not be recognized as a new
charger.
BUG=b:65059574
BRANCH=none
TEST=Boot Fizz on BJ adapter. Verify plugging in Type-C adapter
doesn't shut down the system.
Change-Id: Ie49b128ae64f917a227f9081148565a3f5356212
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655638
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes EC refuse PR swap when the system is powered
through the USB-C port because switching from SNK to SRC will
cause the system to shut down.
BUG=b:65481832
BRANCH=none
TEST=Boot Fizz on USB-C and BJ.
Change-Id: I52c5813adc1ea9b4e69e65599c1794ae43192a1e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655643
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The manufacturer names for the Robo LG and Simplo batteries were
incorrect. Both of them had an '/011' which is not actually part of
the name. This has been fixed. In addition, the ship mode command
needs to be 0x0000 followed by 0x1000, but it was using 0x0000 and 0x0001.
BUG=b:64821365
BRANCH=None
TEST=manual
Tested Celpext, SMP, and LG batteries with EVT systems. Verified that
'cutoff' from EC console and 'ectool batterycuttof' from AP console
caused the battery cutoff to take effect. Also verified the
manufacturer name from the batteries matched the what's stored in the
battery info table.
Change-Id: I48369da4d2c6137b50614b003df57a359a49c4f4
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/662137
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We use address 0x80000000, which is not mapped to anything in
STM32F0 address space.
BRANCH=none
BUG=b:63993173, b:65188846
TEST=./usb_updater2 -p 144.0_2.0.bin
CQ-DEPEND=CL:601814
Change-Id: I9a9044d29ebe058d3792dc984cac4051a005cf8f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/597468
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Chromebox ECs performs EFS: verifying firmware before the AP boots.
This patch updates host commands which are required for the EFS.
The change includes:
* Update EC_CMD_FLASH_REGION_INFO to accept EC_FLASH_REGION_UPDATE
* Update EC_CMD_VBOOT_HASH to accept EC_VBOOT_HASH_OFFSET_UPDATE
When EC_FLASHS_REGION_UPDATE is specified, EC_CMD_FLASH_REGION_INFO
returns the slot which currently is not hosting a running RW copy.
When EC_VBOOT_HASH_OFFSET_UPDATE is specified, EC_CMD_VBOOT_HASH
computs the hash of the update slot. This hash covers the entire
region, including the signature at the end.
This patch undefines CONFIG_CMD_USBMUX and CONFIG_CMD_TYPEC
for gru to create space.
BUG=b:65028930
BRANCH=none
CQ-DEPEND=CL:648071
TEST=On Fizz, verify:
1. RW_B is old and updated by soft sync. RW_B is activated and
executed after reboot. System continues to boot to OS.
2. RW_A is old and updated by soft sync. RW_A is activated and
executed after reboot. System continues to boot to OS.
Change-Id: I9ece907b764d07ce94054ba27996e048c665a80a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648448
In case of battery cut-off on Soraka, there is a battery requirement
that AC power should not be applied for at least 9 seconds after the
cut-off is performed. Performing battery cut-off when battery is at
critical level results in a bad user experience if the user connects
AC power within the 9-second window. Thus, instead of performing a
battery cut-off, make the EC hibernate in critical battery conditions.
BUG=b:64703097
BRANCH=None
TEST=make -j buildall
Change-Id: I40827faccd52c8628b69773cb22ccc6ed19915ed
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656609
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reworked suzy-q and suzy-qable all provide Rp, so there is no need for
special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS
is no longer relevant, since we no longer take special action when VBUS
is seen without Rp.
BUG=chromium:737755
BRANCH=None
TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5.
Also, verify zinger works in S5 on reef.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec
Reviewed-on: https://chromium-review.googlesource.com/656067
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For historical reasons, CCD, reset, and power button control were
scattered around several files. Consolidate the code in more sensible
(in retrospect) places.
No functional changes, just moving code.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50
Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653766
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy.
This change makes EC treat it also as a RW copy.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
- This CL adds the infrastructre needed to support different battery
types for the Coral project.
- This includes adding a battery_check_disconnect common function
that's used folloiwng battery cutoff events to ensure that the
battery is able to provide power before reporting it as present.
When the battery is not present, there is a 1 second delay used
before allowing the battery to report as present. This specific
change is motivated by an issue discovered on Eve which resulted in
H1 power rail issues and could lock up the H1.
https://chromium-review.googlesource.com/c/592717https://chromium-review.googlesource.com/c/585837
- This includes a battery_cutt_off_battery common function that can
be used by all battery types using the register and regiseter data
required for each battery's ship mode.
BUG=b:64772598,b:64728711,b:64821365
BRANCH=None
TEST=manual testing on Coral proto with Sanyo battery and tested on
Nasher with BYD and LGC-LGC.593 batteries. Verified that battery
cutoff command via EC console works. Verified that can start up as
expected following battery cutoff. Also tested battery cutoff
initiated by removing the battery from the system while it's powered
up. Also tested 'ectool batterycutoff at-shutdown' from the AP console
and verifed that battery cutoff was successful following 'apshutdown'
on the EC console.
Change-Id: I9d884efa9d64fb94d46447feb028c5d9ae82a20f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627496
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Servo v4 monitors the SBU lines on USB-C connects in order to determine
which direction to set the orientation of the SBU mux. However, when
there's traffic on the lines, for example when the EC is rebooting, it
can lead to the wrong conclusions and terminate the USB connection.
This commit adds a CCD keepalive console command.
Additonally, when the Type-C cable is unplugged from the DUT for at
least 900ms, the CCD keepalive will be cleared. This is such that if
the cable is unplugged and then replugged in a different orientation,
the detection will still work.
BUG=b:64903997
BRANCH=servo
TEST=Flash servo_v4; `keepalive enable`. Run `dut-control
power_state:reset` > 100 times and verify that the USB connection stays
alive.
Change-Id: I5c8f9ab3361d4f52f906161ab5da471a36725a4e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/647031
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage
their own enabling and disabling of the ports (UART, SPI, etc.) This
is tricky because the rules for when ports should be enabled are
non-trivial and must be applied in the correct order. In additionl
the changes all need to be serialized, so that the hardware ends up in
the correct state even if multiple state machines are changing
simultaneously.
Consolidate all of that into chip/g/rdd.c. The debug command for it
is now 'ccdstate', which just prints the state machines. This will
allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd
open', etc.
Also include UART bit-banging into that state which must be
consistent. Previously, it was possible for bit-banging to leave UART
TX connected, instead of returning it to the previous state.
Use better names for CCD config fields for UART. I'd had them backwards.
BUG=b:62537474
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 image
1) No servo or CCD
Pull SERVO_DETECT low (disconnected)
Pull CCD_MODE_L high (disabled)
Pull EC_DETECT and AP_DETECT high (on)
Reboot. RX is enabled even if cables are disconnected so we buffer.
ccdstate -> UARTAP UARTEC
Pull EC_DETECT low.
ccdstate -> UARTAP
Pull EC_DETECT high and AP_DETECT low.
ccdstate -> UARTEC
Pull AP_DETECT high.
ccdstate -> UARTAP UARTEC
2) Servo only still allows UART RX
Pull SERVO_DETECT high (connected).
ccdstate -> UARTAP UARTEC
3) Both servo and CCD prioritizes servo.
Pull CCD_MODE_L low (enabled).
ccdstate -> UARTAP UARTEC
Reboot, to make sure servo wins at boot time.
ccdstate -> UARTAP UARTEC
Bit-banging doesn't work when servo is connected.
bitbang 2 9600 even -> superseded by servo
bitbang -> disabled
ccdstate -> UARTAP UARTEC
4) CCD only allows more ports and remembers we wanted to bit-bang
Pull SERVO_DETECT low.
ccdstate --> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
Reboot and see we don't take over servo ports until we're
sure servo isn't present.
ccdstate --> UARTAP UARTEC (for first second)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that)
5) Bit-banging takes over ECTX
bitbang 2 9600 even
bitbang -> baud rate 9600, parity even
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
6) Permissions work. Allow easy access to full console and ccdopen:
ccdset OpenNoTPMWipe always
ccdset OpenNoLongPP always
ccdset GscFullConsole always
Default when locked is full AP UART EC RO, no I2C or SPI
ccdlock
ccdstate -> UARTAP+TX UARTEC
No EC transmit permission means no bit-banging
bitbang 2 9600 even
bitbang -> disabled
ccdstate -> UARTAP+TX UARTEC
But it remembers that we wanted to
ccdopen
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
Try turning on/off permissions
ccdset UartGscTxECRx always
ccdlock
ccdstate -> UARTAP+TX UARTEC+TX
No read means no write either
ccdset UartGscRxECTx ifopened
ccdlock
ccdstate -> UARTAP+TX
ccdopen
ccdset UartGscRXAPTx ifopened
ccdlock
ccdstate -> (nothing)
Check AP transmit permissions too
ccdopen
ccdset UartGscRxAPTx always
ccdset UartGscTxAPRx ifopened
ccdlock
ccdstate -> UARTAP
Check I2C
ccdopen
ccdset I2C always
ccdlock
ccdstate -> UARTAP I2C
SPI port is enabled if either EC or AP flash is allowed
ccdopen
ccdset flashap always
ccdlock
ccdstate -> UARTAP I2C SPI
ccdopen
ccdset flashec always
ccdset flashap ifopened
ccdlock
ccdstate -> UARTAP I2C SPI
Back to defaults
ccdoops
Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/615928
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
There is no point in updating the Cr50 to an image which will not be
allowed to run due to board ID settings mismatch.
This patch modifies the prototype of check_board_id_mismatch() to
allow to pass to this function an arbitrary pointer to an image
header, so that the function can check not only the image in the flash
memory, but also the image which just arrived over the line.
The contents_allowed() function now checks if the new image is
compatible with the Board ID value in Info1 and rejects the new image
if there is a mismatch.
BRANCH=cr50
BUG=none
TEST=tried updating a Cr50 to an image which is incompatible with the
Info1 fields contents. The update attempt is rejected. Verified
that updating to a compatible image still works as designed.
Change-Id: I3d6c16df11fcabd05888f3cbf5e9a81dc51fe66f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/650812
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The state machine in common/case_closed_debug.c only handles a subset
of what we need to do for Cr50 external case closed debugging, and
also supports a 'partial' CCD state that doesn't exist for Cr50. Move
the few lines of code from that we actually need into our file.
BUG=none
BRANCH=cr50
TEST=manual
Assert CCD_MODE_L
See 'CCD EXT enable'
Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint
Confirm firmware update over USB works
Deassert CCD_MODE_L
See 'CCD EXT disable'
Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint
Confirm firmware update over USB does not work (can't find device)
Change-Id: Id96f2770632839a9690740ece54bc2eb71d39a38
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/647909
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, only usb_pd_protocol.c cares about the actual ccd mode
(disabled/partial/enabled). Everything else just cares whether it's
enabled or not. So promote the boolean ccd_is_connected() from
board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to
match the new nomenclature (since 'CCD' itself is now too overloaded).
This will make it easier to handle CCD state directly in board/cr50
after we split it from common/case_closed_debug.c
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50; make sure USB endpoints still work
Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648212
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, chip/g/rdd provided a method for an external console
command to override the Rdd cable detect state. But since we'll be
refactoring the 'ccd' command, it's tidier to move this to a console
command inside the rdd driver itself.
BUG=none
BRANCH=cr50
TEST=manual, with no debug cable present
rdd enable -> Rdd connect
rdd -> keepalive
rdd disable
rdd -> connected (hasn't had a chance to run state machine)
(wait <1 sec)
rdd -> debouncing
(wait 1 sec) -> Rdd disconnect
Change-Id: I141eedf8070b4ad2c96cc5a364f4e37dc29bed70
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/647991
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
