This patch implements the board_hibernate() function for
poppy. When running on battery only and in G3 state, the board
should transition into PG3 after CONFIG_HIBERNATE_DELAY_SEC
BRANCH=none
BUG=chrome-os-partner:61098
TEST=Disconnect AC. Use hibernate command from EC console to put
system into hibernate. Wake up the system from hibernate using
power button press or AC insert. Alternatively Use hibdelay command
to specify the hibernate wait timeout. Put the system into G3.
After hibdelay seconds the board should hibernate.
Change-Id: Ie0fc10ad60f15d6f40cf46bbe8b6dc9493c19e79
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/446242
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add the option to use the PLL connected the 16Mhz HSI oscillator.
Fix the system timer pre-scaling when changing frequency:
- we need to generate an update event immediately as on a 32-bit timer it
might take a very long time before going an actual update event.
- we need to ensure that the OS timestamp is monotonic and sensible
across the frequency jump.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=manual, on STM32L4 console, do several gettime and compare against
wall time, switch to 80Mhz with 'clock pll', verify again gettime
against wall clock.
Change-Id: Ibddbd46173b7594d16fb07e4b57660a50c636568
Reviewed-on: https://chromium-review.googlesource.com/445776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This is the recommended futility signature type for new boards.
BRANCH=none
BUG=chromium:690773
TEST=Flash hammer, RW image checked correctly
TEST=futility show --type rwsig \
--pubkey build/hammer/key.vbpubk2 build/hammer/ec.RW.bin
Change-Id: Id8648199891fdd4df63ecb599e0c5e927bc861d0
Reviewed-on: https://chromium-review.googlesource.com/441549
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cr50 on x86 will run normally enter deep sleep and then wake up
immediately. When the AP turns off it stops pulling up the i2cs signals.
When cr50 enters deep sleep it sees that the i2cs signals are low then
wakes up immediately. After resuming cr50 will remain awake for 20 then
enter deep sleep. At this point it will remain asleep.
This change disables i2cs_sda and scl as wake pins when entering deep
sleep. Just like ARM these tpm signals are not in use when the device is
off. We have other signals to detect when the system leaves s3 or s5, so
we should rely on those.
We need this change because we want cr50 to fully enter deep sleep when
we run suspend resume tests. Right now the AP does not sleep long enough
for cr50 to enter the second deep sleep.
BUG=none
BRANCH=none
TEST=turn off the AP and make sure cr50 doesn't resume from deep sleep
immediately. run suspend_stress_test -c 5000 and verify cr50 enters deep
sleep and resumes correctly. verify dioa9 and dioa1 are enabled as wake
pins on resume
Change-Id: Ided8b2b7d5455650bca1e8d781063d092fb74c43
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443389
Added interrupt handler for CABLE_DET signal on both port 0/1. This
allows us to define CONFIG_USB_PD_TCPC_LOW_POWER.
BUG=chrome-os-partner:63067
BRANCH=none
TEST=Connected USB mouse, keyboard and USB stick to both ports and
verified the devices were recognized and attached properly. Verified
that ports 0/1 always worked with blackcat typeC charger.
Change-Id: I4d8a8bdba4f95e73333e2e01f11fe1d48453a2fe
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444315
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Added Si114x light sensor to the motion sense struct and enabled it in
polling mode. Also added backward compatibility for the ALS to report
readings via ACPI.
BUG=chrome-os-partner:61470
BRANCH=none
TEST=Enter 'accelinfo on 1000' on the EC console and verify light
readings are present and they increase/decrease as the light pointed
to the sensor changes. Also verifed with AIDA64 app in arc++
Change-Id: I22e0b87034150d2e987987da053de3c312fcc98b
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440378
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Currently, manually triggered reboots cause the retry counter to be
incremented. However, if the system is responsive enough to process the
reboot commands from either the console or TPM vendor command, we can
assume that the image is "ok". This commit changes the Cr50 behaviour
to decrement the retry counter when a reboot is issued on the console or
the TPM vendor command is received.
BUG=chrome-os-partner:62687
BRANCH=None
TEST=Flash cr50. Flash an older image in the other slot. Enter the
reboot command on the console over 10 times and verify that retry
counter never exceeds RW_BOOT_MAX_RETRY_COUNT and older image is never
executed.
CQ-DEPEND=CL:444264
Change-Id: Ic35bdc63c4141834584a00a7ecceab2abe8dfc21
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443330
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The matrix was not correct and sensor would report -1G along the Z axis
while on a flat surface.
BUG=chrome-os-partner:63021
BRANCH=none
TEST=Check in ARC++ AIDA64 the gravity data is reported correctly along
the Z axis.
Change-Id: I0ddbf40876746432c640f547a5efede3a07c6eec
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444066
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Rajat Jain <rajatja@chromium.org>
As the new form-factor has the lid accelerometer on the
reversed side facing the B-cover, the matrix setting
depending on board version; in such matter, it should be
able to compatible with old version of boards.
We create a new hook function for board specific tweaks,
this is because since the commit of 0c57824
("reef: Re-factor PP5000 and PP3300 enable/disable"),
the board_init() is no longer a good place for tweaks,
because ADC read should come after adc_init();
such that, new hook ensures robust ADC reading which is
the source of board version.
Also, we fix an arithmetic error for version-3 workaround,
i.e. patch the commit of ca99f38 ("snappy: BMI160 is
powered down on board v3 and older in S3"), else it could
trigger unexpected EC panic like this:
[89.770776 chipset -> S3]
[89.771222 power state 2 = S3, in 0x006d]
[89.772428 I2C unwedge failed, SCL is being held low]
[89.773775 TCPC p0 Low Power Mode]
[89.812962 Reset i2c 01 fail!]
...snip...
[91.816415 Unexpected i2c state machine! 1]
Time: 0x00000000057a7d9c us, 91.913628 s
Deadline: 0x00000000057a8a1d -> 0.003201 s from now
...snip...
Rebooting...
--- UART initialized after reboot ---
[Reset cause: soft]
...snip...
BUG=chrome-os-partner:62676
BRANCH=reef
TEST=check the DVT1 and DVT2 unit rotate normally.
Change-Id: Ic53e67e0c97e57056587adb6b260e81c0f99437a
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/442252
Commit-Ready: Chen Wisley <wisley.chen@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
usbpd1 futility image type is deprecated and should not be used for
new designs. This adds proper support for rwsig image type.
Key and signatures are added at linker stage step (futility cannot
directly create such signed images). Thanks to VB21 header, rwsig.c
can now tell how many bytes of the RW image need to be
cryptographically verified, and ensure that the rest is blank (0xff).
BRANCH=none
BUG=chromium:690773
TEST=make BOARD=hammer; flash, RW image is verified correctly.
TEST=make runtests -j
TEST=For the rest of the tests:
Change config option to CONFIG_RWSIG_TYPE_RWSIG
TEST=make BOARD=hammer; flash, hammer still verifies correctly.
TEST=cp build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig;
futility sign --type rwsig --prikey build/hammer/key.vbprik2 \
build/hammer/ec.RW.bin
diff build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig
=> Same file
TEST=Add CONFIG_CMD_FLASH, flashwrite 0x1e000, reboot, EC does
not verify anymore.
TEST=dump_fmap build/hammer/ec.bin shows KEY_RO and SIG_RW at
correct locations.
Change-Id: I50ec828284c2d1eca67fa8cbddaf6f3b06606c82
Reviewed-on: https://chromium-review.googlesource.com/441546
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable CONFIG_USB_PD_TCPC_LOW_POWER, and add cable detection handling.
BRANCH=none
BUG=chrome-os-partner:62964
TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter:
keyboard works; charging works
Change-Id: I0751cc7b5fc8ba71388f08b7001c0daceda37bb6
Reviewed-on: https://chromium-review.googlesource.com/443747
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Use the motion sensor to manage ALS as well.
The current interface (via memmap) is preserved, but
we can also access the sensor via cros ec sensor stack and
send the ALS information to ARC++.
BUG=chrome-os-partner:59423
BRANCH=reef
CQ-DEPEND=CL:424217
TEST=Check the sensor is working via ACPI sensor and
cros ec sensor. Check ARC++ sees the sensors.
Change-Id: Iaf608370454ad582691b72b471ea87b511863a78
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There are two batteries being evaludated for Eve and there needs to be
a batteery_info struct for each one for situations where the gas gauge
can't be read and the charge state machine uses these parameters.
BUG=chrome-os-partner:62711
BRANCH=none
TEST=Verifed that battery_type is read correctly for both LG and
LISHEN battery units.
On Lishen unit Drain battery completely, then reconnect type C
charger. Verified that battery is now charging. Prior to this CL, the
LISHEN bat would not charge because the internal overcurrent protection
mode would not tolerate the 256 mA precharge current that's specified
for the LG battery.
Tested that both Lishen and LG recovered after forcing a battery
disconnect.
Change-Id: I201eaf61ad03d3dc0d199ab441b07c371bceddde
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440514
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With this change, only DEV images will have the capability to unlock the
Cr50 console.
BUG=chrome-os-partner:62727
BRANCH=None
TEST=Build a prod image, flash Cr50, try to unlock the console. Verify
that access is denied and console remains locked.
TEST=Attempt to read EC and AP flash over ccd. Verify that it fails.
TEST=Remove AC and battery. Plug in AC. Verify that console is still
locked.
TEST=Plug in AC, unplug battery, verify that write protect is disabled.
Verify that console is still locked and cannot be unlocked.
TEST=Build a dev image, verify that console can be locked and unlocked.
Change-Id: Ic47aa34f42ee295e74ba3a40b709ac42c34a30b7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439764
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The trackpad interrupt is input only to the EC and should not ever
be driven from here.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on eve p1
Change-Id: I3ffa2ddb4990550b57c9191b5d721ab0ba206aca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439829
Poppy uses SPI, Plt_Rst, and USB to AP. Its strapping option is 1M PU
on both DIOA9|DIOA1 which gives it a strap_config value of 0xA.
Rowan uses I2C and it's strapping option is 5k PD on DI0A12 and 5k PU
on DI0A6 which gives it a strap_config value of 0x30.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Used H1 dev board with external PU/PD resistors to replicate both the
Poppy and Rowan configurations.
With Poppy config console shows:
[0.004468 Valid strap: 0xa properties: 0x45]
With Rowan config console shows:
[0.004460 Valid strap: 0x30 properties: 0x2]
Change-Id: I569960114c6f1844a55912fbf7f3d97008f9f71f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428000
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This removes CONFIG_USB_PD_TCPC_FW_VERSION.
board_print_tcpc_fw_version is removed since it's no longer called.
PD chip info is printed in usb_pd_protocol.c.
BUG=none
BRANCH=none
TEST=buildall. Boot Electro, verify chip info is printed.
Change-Id: I2ff860c2a1b17ceea124644ba8feb356b9cca2eb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434911
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added code to put the ANX74xx in low power mode for different DRP state.
1. When nothing attached or system is in S3 or S5 disable the auto
toggling and put ANX74xx system in Analog control mode.
2. Using the CABLE_DET interrupt pin (attach event) enable normal power
mode.
BUG=chrome-os-partner:59841, chrome-os-partner:61640
BRANCH=None
TEST=Manually tested on Reef using below dut-control command
dut-control pp3300_pd_a_mw -r <n>
1. S0, S3, S5 - Nothing connected, ANX in low power mode.
2. In S0 SNK (display/USB dongle, eMark cable) connected & put
system to S3, ANX remains in normal mode.
3. In S0 SNK connected & put system to S5, ANX in low power** mode.
4. In S0 nothing connected, put system to S3 or S5, attach
SNK, ANX in low power** mode.
5. Attach SNK at S3/S5 & boot to S0, ANX in normal mode.
6. SRC (AC adapter) with/without eMark cable are detected in
S0, S3, S5, and continue to charge the system after S-state
transition.
low power**: ANX74xx hardware limitation that Ra/Open (Ex: E-Mark cable
only) detection will trigger CABLE_DET continuously, therefore ANX74xx
will go to normal power mode momentarily and then low power mode in a
loop.
Change-Id: I30f7fd7a85e31987fb77e2cab2fe140d59dd3629
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/415580
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Electro is able to boot on 15w to Depthcharge but requires 18w or above
to boot to the logon screen. This patch allows 15w charger to boot
Electro to Depthcharge (as before) but prevents it from booting after
that unless the EC in RW negotiates with the charger and gets 18w or
more.
Without the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge proceeds then browns out
4. Boot without battery
5. Reboot by FSP for RTC well drop
6. Charger goes to disabled state
7. EC fails to negotiate with charger, hard resets charger
8. Brownout
9. Repeat from #4
With the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge times out and shuts down the system
So, the outcome is same. With the patch, the user at least is (or will
be) given a chance to know battery is the problem. I suppose we have to
add a screen showing battery is drained or dead. I currently see no
such code in vboot_select_and_load_kernel.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chrome-os-partner:61801
BRANCH=none
TEST=Hack the code to enforce syslock. Disconnect battery.
Use 18w charger to boot the system. Use 15w charger not to boot.
Change-Id: I00d79a96221f1d3b8c6d529de9b8e4588d6112aa
Reviewed-on: https://chromium-review.googlesource.com/440390
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current fast charge assumes only one battery voltage threshold range for
charger profile override. However we have multiple battery voltage
threshold ranges for few batteries hence added a code which can consider
multiple battery threshold ranges and choose respective charge profile.
BUG=chrome-os-partner:62653
BRANCH=none
TEST=Manually tested on Electro. Manipulate smp_cos4870 & sonycorp
battery voltage & temperature ranges and observed correct charge
profile is selected.
Change-Id: Icddc047e608cc8f63cd0c19be716e0f7908ca715
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/438804
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Take in account that sensors are down in S3, reinit them back when
moving from S3 to S0.
Do this only for board version 3 and older. board v4 will have
sensors powered in S3.
BUG=chrome-os-partner:61502
BRANCH=reef
TEST=Check EC power sensors up coming from S3 to S0:
[1.627437 power state 6 = S3->S0, in 0x00cf]
[1.627994 Port 80: 0x1001][1.628600 chipset -> S0]
[1.637391 TCPC p1 Low Power Mode]
[1.645020 Lid Accel: Done Init type:0x0 range:2]
[1.647733 Lid Accel ODR: 10000 - roundup 1 from config 1 [AP 0]]
[1.649015 TCPC p1 Low Power Mode]
[1.662231 TCPC p1 Low Power Mode]
[1.670560 Base Accel: MS Done Init type:0x0 range:2]
C0 st15
[1.679813 PB task 6 = released]
[1.680783 PB PCH pwrbtn=HIGH]
[1.681108 PB task 0 = idle, wait -1]
[1.683463 Base Accel ODR: 10000 - roundup 1 from config 1 [AP 0]]
[1.686275 Base Gyro: MS Done Init type:0x1 range:1000]
[1.697973 Base Gyro ODR: 0 - roundup 0 from config 0 [AP 0]]
[1.776627 Base Mag: MS Done Init type:0x2 range:2048]
[1.786490 Base Mag ODR: 0 - roundup 0 from config 0 [AP 0]]
...
Change-Id: Icb9961a0f3ce1b478c47057716211e6e14c13674
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428125
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 37e6fb246495ac972e0bc4ff6fcc16b9bf2eee7b)
Reviewed-on: https://chromium-review.googlesource.com/440511
Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
x86 devices use TPM_RST_L to detect the AP state, so we set
device_states[DETECT_AP].detect to GPIO_TPM_RST_L on those boards.
board_update_device_state uses this signal to poll the AP state once a
second to detect if the device is off.
If for some reason TPM_RST_L is deasserted, but the tpm reset handler
has not yet set the state to 'on', we will catch it when we poll the AP
state with board_update_device_state. It will call device_state_on with
TPM_RST_L. In that case device_state_on used to silently disable the
TPM_RST_L interrupt and not change the AP state. This change modifies
device_state_on to notify the tpm reset handler and prevent it from
disabling the tpm reset interrupt.
BUG=chrome-os-partner:62748
BRANCH=none
TEST=disable the deferred_tpm_rst_isr call in
configure_board_specific_gpios. Close the lid and wait 5 minutes. Open
the lid. Verify cr50 prints "device_state_on: tpm_rst_isr hasn't set the
AP state to 'on'" and the system boots normally.
Change-Id: I6e5b722fab6e7b0acb91dda0e5207e4411e97363
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439816
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a host command to get PD chip info.
For PS8751, tcpci_get_chip_info will fail if the chip is in
low power mode. It can be woken up by reading a random register
first then wait for 10ms.
This code doesn't have the wake-up read to avoid 10ms delay.
Instead, we call this function immediately after the chip is
initialized because it'll gurantee the chip is awake.
Once it's called, the chip info will be stored in cache, which
can be accessed by tcpc_get_chip_info without worrying about
chip states.
localhost ~ # ectool pdchipinfo 0
vendor_id: 0xaaaa
product_id: 0x3429
device_id: 0xad
fw_version: 0x15
localhost ~ # ectool pdchipinfo 1
vendor_id: 0x1da0
product_id: 0x8751
device_id: 0x1
fw_version: 0x37
BUG=chrome-os-partner:62383
BRANCH=none
TEST=ectool pdchipinfo 0/1. make buildall
Change-Id: I3f1667d00ce1826936d90882ada1df6ed6b0ea37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433166
This commit changes the Cr50 write protect behaviour to simply follow
the state of the battery present pin. The state can still be overridden
both ways by using the `wp` console command. A user can either force
write protect enabled or force write protect disabled. Additionally,
the behaviour can be reset to follow the state of the battery pin by
issuing `wp follow_batt_pres`. However, the ability to force the write
protect state requires an unlocked console.
BUG=chrome-os-partner:62726
BRANCH=None
TEST=Plug in battery, verify that WP is enabled. Plug in AC and unplug
battery, verify that WP is disabled.
TEST=Unplug battery, unplug AC, plug in AC, verify that WP is disabled.
TEST=Unplug battery, verify that WP is disabled. Use `wp' command to
enable WP, verify that it is enabled.
TEST=Plug in battery, disable WP using `wp` command, put cr50 into deep
sleep, wake it up, verify that WP is still disabled.
TEST=Plug in AC, plug in battery, disable WP using `wp` command, unplug
and plug battery connector, verify that WP is still disabled.
Change-Id: I83d9820067800801ddbde311eab0853c3c2216d3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
After configuring tpm_rst_l to be connected to the correct pin, check
the level of GPIO_TPM_RST_L to make sure we did not miss the rising
edge. If we did then call the tpm reset handler
BUG=chrome-os-partner:62748
BRANCH=none
TEST=verify electro boots, close the lid, wait 5 minutes, open the lid
and verify it still boots
Change-Id: I1a229fa53664767f0e5cad5f80285f5f030f2197
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439879
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
