Provide a function which is called when keyboard scan data is ready,
and make it do the right thing.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I0089a7ff78ba035ba6648220ae2e03a958d444d8
We want to use this for drivers, so start it up on boot.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: Ie69fb9d6df75150dd3903fe37a9b72c0a663f045
Signed-off-by: Simon Glass <sjg@chromium.org>
Add nopll command to turn off the PLL, reducing the system clock to 16Mhz.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8798
TEST=manual
boot system
press power button to boot x86
temps // should print all temperatures
timerinfo
timerinfo
timerinfo // convince yourself this is counting up at about 1MHz
nopll // this drops the system clock to 16MHz
temps // should still print all temperatures
timerinfo
timerinfo
timerinfo // should still be counting up at about 1MHz
Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
De-assert the lightbar reset GPIO to be able to access its registers.
According to the HW guys, it will consume less power in standby than in
reset due the pull-up on the reset line.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
BUG=None
TEST=manual
On Link proto-1, type "lightbar test" in the EC console and see it blink.
On BDS, just build it. Nothing actually changes for BDS.
Change-Id: I9ec612c80f48d41ccf779f0962fc047966d4b7ba
Servo2 can set the write protect signal
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8580
TEST=manual
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:on
Then from EC console:
gpioget WRITE_PROTECTn
0 WRITE_PROTECTn
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:off
Then from EC console:
gpioget WRITE_PROTECTn
1* WRITE_PROTECTn
Change-Id: I9976cd6f114c8dae75434adf99d9409107b6ada0
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
We moved a while ago to a table of ADC channels, so having a
meaningless constant defined in board.h is more harmful than helpful.
BUG=none
TEST=build link, bds
Change-Id: I651a609c9ed13f879bb943c90731275407d77e50
Signed-off-by: Randall Spangler <rspangler@chromium.org>
The kernel no longer uses port 80 as a delay mechanism, so we don't
need to detect the no-longer-present spammy writes.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7972
TEST=port80 scroll, then boot the system. see a few repeated bytes,
but not piles of 00 and ff's.
Change-Id: Id14dc43ab4e1b15c6bab99a17c062f295a59e7e6
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
This CL adds a charge state machine for SMB compliant battery pack.
Vendor specific charge constraints can be applied through function
call, defined in battery_pack.h .
BUG=chrome-os-partner:7526
TEST=Attach EC serial console
Unplug AC adapter: state ==> "discharge"
Plug AC adapter: state ==> "charge"
Battery full: state ==> "idle"
Unplug battery: state ==> "error"
Change-Id: Iabff0988a6067d37c17c11b060bbb7e66505c118
The thermal engine monitors the temperature readings from all sensors.
For each sensor, five threshold temperatures can be set:
1. Low fan speed.
2. High fan speed.
3. SMI warning.
4. Shutdown CPU.
5. Shutdown everything we can.
Each of these thresholds can be set to either a fixed value or disabled.
Currently the real implementation of SMI warning and shutting down is
left as TODO, as indicated in the comment.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manually change threshold value to test all actions can be triggered.
Change-Id: If168dcff78ef2d7a3203cb227e1739a08eca961e
Add a task to update fan speed in LPC mapped memory once per second.
Also added read_mapped_mem16 and read_mapped_mem32.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8183
TEST="ectool pwmgetfanrpm" shows same result as "faninfo" from ec
console.
Change-Id: Ibc536acd39f836ffcad0bfa7c9c14e730220bd49
On bds, always send the keyboard scan code for the power button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I56ad8c9dd67edfd54190d64f16742896a86b9ac1
The PMIC_ACOK signal is active-low.
Let's drive it correctly.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On ADV board, check that a short key press on the power button is
now able to start the board
Change-Id: Iea71939aeb532618019a9e7774721703c632976f
Set the keyboard GPIO interrupts and task for the Daisy and ADV boards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy
run EC firmware on ADV board.
Change-Id: I01c7f0112b7ab3382e04ad032a86fb0f3878b02b
A temperature polling task is added to achieve temporal correction and
also reduce the latency of reading temperature.
Factor out sensor specific part to keep code clean.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7801
TEST=On link, 'temps' shows all temperature readings.
Cover each sensor with hand and see object temperature rise.
Compilation succeeded on bds/adv/daisy/discovery.
Change-Id: I3c44c8b2e3ab2aa9ce640d3fc25e7fba56534b86
This loosely ports the LM4 keyboard_scan code to STM32
Notable differences:
- Keyboard GPIO layout is spread across multiple ports and is not
contiguous in many places. Because of this, bitmasks are mostly
generated on-the-fly instead of hard coded (IO is kept to a minimum)
- Longer timeout when scanning columns (100us versus 20us)
Also, some functions are stubbed out currently since they rely on
other bits being implemented:
- keyboard_state_changed()
- keyboard_has_char()
- keyboard_put_char()
BUG=none
TEST=Tested on STM32L-Discovery (monitoring keystrokes via UART)
Change-Id: I84985879589e70688b2b29b288ab17037f7668b2
Compared to Daisy, it has the EC console on USART2 (pins PA2 and PA3)
and regulator enable GPIOS EN_PP1350 and EN_PP5000 are on PA9/PA10.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy && make BOARD=discovery
Change-Id: I545f7c9b05480e58db913ea562c77a1a1cd2b11c
Avoid duplicating in each board file, the stub functions replacing not
implemented drivers on the STM32L platform.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery
Change-Id: I25cd949c31e53a90c39f623617c7d52517a3d205
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
This should be enough to switch on the board from either the power
button or the EC console.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run Daisy firmware on Discovery board with logic analyzer attached
to GPIO pins. With an added task to simulate PMIC startup and AP
startup, check the timing chart looks good.
Change-Id: I5dfeab05d0481d121ddacb36b69a542cc1bd428c
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
The order of the GPIO in the header was not matching the signal list.
EC_INT is an output to trigger an interrupt on the application
processor.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy
Change-Id: Ib0eb675ad7d7e9e105b1d486c181a6df9bd5ad9b
When we are not running the ROM monitor first, we must set the pins used
for USART1 (PA9/PA10) as alternate function.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=Run firmware on the discovery board not from the monitor and see
the traces.
Change-Id: I32be3d5a88a3e71828d081d74503722331a649b8
Necessary files to build it and GPIO definitions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery && make BOARD=link
Change-Id: I22ad8d2d859f9c884bf2e3f92db02d992ad669a6
BUG=chrome-os-partner:7839
TEST=none, work in progress
Change-Id: I20acde8db7f250227adcd4b9dc59328362e68720
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Remove id field from temp_sensor_t struct, since it's only used by the
console command (which already knows the id, because it's looping over
it).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='temps'
Change-Id: I0970850073d644509cd5501d7ac4421c7373143b
This change adds a common part of smart battery driver. Following
features are not implemented, or in chip specific driver:
Battery access control, authentication, factory mode
Manufacturer access/data commands
Block read/write, device name, flash data
Chip specific features, per cell info/temp/capacity
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7856
TEST=console command check battery staus
[unplug power]
> battery
[check voltage,current,capacity,time to empty]
[plug power]
> charger voltage 8400
> charger current 4250
> battery
[check current,time to full]
> charger input 4032
> battery
[check current,time to full]
[wait 130 seconds, charger watch dog timeout]
> battery
[check current]
Change-Id: Ifac17a0892f52e8f37eebc14b00e71f18360776c
Signed-off-by: Rong Chang <rongchang@chromium.org>
