Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8971
TEST=manual
waitms 1500
(see watchdog trace)
waitms 1500
(should see watchdog trace again)
waitms 3000
(should see trace, then system should reboot)
Change-Id: Ieb5009d7a7bc9e1ed795e58efb0cb44a1eeb2706
Fix some mistakes in previous commit. Modified some comments and moved
guard value initialization to a more readable place.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8069
TEST=Compile with detection enabled. Cause a task to overflow and see
device halted. Hook gdb and see it stopped at the assertion.
Change-Id: I608ee9aec3fda8c3945e1874d4bbb2c4ae1fc6dd
Use guard value to detect stack overflow
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8069
TEST=Compile with detection enabled. Cause a task to overflow and see
device halted. Hook gdb and see it stopped at the assertion.
Change-Id: I3417cca8edf4e1291ccb7848bd564b631a9ce463
Add nopll command to turn off the PLL, reducing the system clock to 16Mhz.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8798
TEST=manual
boot system
press power button to boot x86
temps // should print all temperatures
timerinfo
timerinfo
timerinfo // convince yourself this is counting up at about 1MHz
nopll // this drops the system clock to 16MHz
temps // should still print all temperatures
timerinfo
timerinfo
timerinfo // should still be counting up at about 1MHz
Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7461
TEST=manual
make BOARD={bds,link,daisy}
make tests
flash link system and make sure it boots
Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
The re-scheduling is protected by increasing our priority to -1,
according to ARMv-M architecture manual, we need an ISB after setting
the faultmask register to ensure that the new priority is visible.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8492
TEST=run on proto-0.5 and see that the temperature sensor and battery
tasks are longer hanging (see the bug for details how to check it)
Change-Id: Ia55859cf5c9101a09c61be7647a920126fc0a3b9
When updating the lock field of the mutex to acquire it, if the store
exclusive fails, we want to retry immediatly else if the failure has
been triggered by the other user doing the mutex_unlock we might not be
woken up.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8492
TEST=run on proto-0.5 and see that the temperature sensor and battery
tasks are longer hanging (see the bug for details how to check it)
Change-Id: I0c8a4e997666a7781b3837f0dbbc47ffbc06b6c3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8350
TEST=manual
Hack a task function to return. Then see that it prints an error to
the debug console and the EC continues running, instead of seeing a
hard-fault.
Change-Id: Iacd2b83c4d4845bb8e6c61e07c3150df8edc7e49
Add build information (date/time/builder) which can be displayed at the
EC console.
Generate a version from the board name and the branch tag.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:27013
TEST=on BDS, run version command on the console.
inspect the built binary.
Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
The temperature calculation currently uses fixed point operations.
Change it to use floating point for better readability and maintenance.
Also changes disable_fpu() to accept parameter which serves as
optimization barrier to prevent floating point operations after
disabling FPU.
BUG=chrome-os-partner:7801
TEST=In console, tempremote "tempremote 29715 -105000 6390" gives 28506.
Change-Id: Ib766904b8feb9a78eac9f7cd53afeca85091c5a5
Signed-off-by: Vic Yang <victoryang@chromium.org>
Add an arch include folder. Implement sqrtf for Cortex-M in math.h.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: Ib7b480b6a0bf7760f014a1f73df54673a9016cb6
Signed-off-by: Vic Yang <victoryang@chromium.org>
Implement enable_fpu() and disable_fpu().
enable_fpu() disables interrupt and then enables FPU.
disable_fpu() disables FPU and enables interrupt.
Also added a CONFIG_FPU flag.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521
Signed-off-by: Vic Yang <victoryang@chromium.org>
Preparatory work to introduce a second SoC : 2nd series 2/4
Avoid introducing platform specific dependencies in common files where
they are not necessary.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS and Link
Change-Id: If2ccd022e4956425222b55a5a48ca7522857e7f0
Preparatory work to introduce a second SoC : 2nd series 1/4
The atomic operations are SoC independant since they are only using
LDREX/STREX instructions which are just core specific ARMv7-M).
The watchdog header defines the API which is common to all platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Preparatory work to introduce a second SoC : 5/5
All Cortex-M3/4 have the same NVIC registers at the same address.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
Preparatory work to introduce a second SoC : 4/5
Allow to use the common code for most SoC.
Also simplify the UART code, we don't need speed on the panic path.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=trigger a panic and check the UART output on BDS
Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
Preparatory work to introduce a second SoC : 3/5
We split the drivers files which contain SoC specific drivers from the
OS files which only depend the actual CPU core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and test a few commands on the console.
Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
