Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
It's not safe to sysjump with a DMA enabled as it can led to memory
corruption after we have landed in the new image before that piece of
hardware is re-configured.
Implement and call dma_disable_all() on all platforms with generic DMA.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=chrome-os-partner:34865
TEST=on various boards, call "sysjump rw".
Change-Id: I2a6b63ff19c2d932a5e31bc375bf468bc8ae5125
Reviewed-on: https://chromium-review.googlesource.com/237340
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This conversion is needed in files outside of system.c, so add a new
function.
BUG=chrome-os-partner:34599
TEST=Manual on samus_pd. Run "pd 0 info" and verify "Image RW" is
printed.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia905ba9cf985f3714fa75c81670b8a39e9608f3d
Reviewed-on: https://chromium-review.googlesource.com/236980
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Before sysjump we need to send a soft reset to any attached devices
and then disable PD communication so that we don't re-negotiate again
before the sysjump. This will guarantee expected message ID is cleared
for after the sysjump.
This also moves executing soft reset from before sending the soft reset
command to after the port partner accepts a soft reset.
BUG=none
BRANCH=samus
TEST=test on samus. without this change, when sysjumping the PD MCU
has time to re-negotiate (at least partially) before the sysjump, which
causes various problems. with this change, when sysjumping, the PD
MCU sends soft reset, and then does not send anything else.
Change-Id: Id7a60c62c8908ee4ab33dfbe995ef136b0aa83de
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233751
Fix potential bug in pd_soft_reset() function. That function is
part of a global API and as such can be called by other tasks.
For example, a sysjump which takes place as part of host command
task. So, this function should not directly initiate PD communication
because if it is interrupted by the PD task, then there will
be unpredictable behavior since the send_validate_message() is not
designed to be re-entrant for a given port.
This changes pd_soft_reset() to simply change the PD state to
SOFT_RESET and then wake up the task to actually send the command.
BUG=none
BRANCH=none
TEST=you can test this with a type-C to A receptacle dongle. The
dongle has a pulldown on the CC line, but no device to respond to
PD comms. When you plug in C to A cable, samus should send source
cap repeatedly for 5 seconds. During that time, if you do a sysjump
from RO to RW, it will call pd_soft_reset(), which will send the
soft reset command. But, since there is no device it will timeout
and retry 3 times. During that period, the PD task will wake up
and try to do it's own thing, causing craziness and eventually a
hang and watchdog reset.
With this fix, I can plug in a C to A adapter, and sysjump to RW
cleanly.
Change-Id: Icab936ab8ab930e8e37b5a23825f7f054a50c177
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219893
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Hibernate is not supported on STM32F0. Disable system hibernate so that
the system doesn't auto-reboot after an hour in G3. This also benefits
us in terms of firmware size.
BUG=chrome-os-partner:31665
TEST=Boot on Ryu. Check 'hibdelay' and 'hibernate' commands are absent.
TEST=Boot Ryu from G3.
TEST=Change default hibernation delay to 1 second. Put system in G3.
Check it does not reboot.
BRANCH=None
Change-Id: Ia01d2d74bc5c22c01e29e5877bd4bd38ee7dddc8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214834
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Add BOARD_VERSION_EVT for rev 3 boards
- Rename CAPSENSE_INT_L to ALS_INT_L
- Rename PP3300_ACCEL_EN to PCH_RTCRST_L
- PD_MCU_INT is inverted, remove internal pull and set INT on rising edge
- USB_MCU_RST is inverted
- USBn_ILIM_SEL are inverted
- Enable CONFIG_USB_PORT_POWER_SMART_INVERTED
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=emerge-samus chromeos-ec, not used until EVT
Change-Id: I01521a55a20a230d6d4f929974112c6452c98271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213744
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Software sync on the AP will ask the EC to reboot to RO after the AP
shuts down. This allows the AP to do a clean shutdown before the EC
reboots. The PD chip should be rebooted at the same time the EC
reboots itself, so that in a low-battery case the requested PD reboot
also takes place after AP shutdown.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=From the EC console, 'reboot hard' also reboots the PD chip.
Change-Id: I109a495ca32ad1ac4aac42708935962d3226792e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210570
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On sysjump, we are losing all of our PD states. Instead of trying to
remember all the states and deal with on-going transmission, let's just
issue a soft reset so that the communication starts over.
BUG=chrome-os-partner:31207
TEST=With Ryu/Zinger, do 'sysjump rw' and check EC doesn't reboot.
BRANCH=None
Change-Id: I8779b74491a402434931b3455fa93ff2e178cb1f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212123
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Previous assumption assumed that the flash was remapped
to address 0.
This is not the case anymore since cl/210063
BUG=chrome-os-partner:30997
TEST=Check we can boot the EC now.
BRANCH=None
Change-Id: I46e1dc0ad840b21661aa5d87817369b29a659c9b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210407
Our code base contains a lot of debug messages in this pattern:
CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n")
The strings are taking up spaces in the EC binaries, so let's refactor
this by adding cprints() and ccprints().
cprints() is just like cprintf(), except that it adds the brackets
and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...)
This saves us hundreds of bytes in EC binaries.
BUG=chromium:374575
TEST=Build and check flash size
BRANCH=None
Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200490
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sometimes the toolchain tries to put a relocation which is not suitable
to access variables in a read-only section.
The nds32 gcc uses GP-relative signed 17-bit relocation to access
variables stored in .rodata (eg lwi.gp $r0, [ +gp ])
That's wrong since $gp is pointing in the middle of .data and .bss in
the SRAM, while .rodata is sitting in flash.
Since on IT8380, the flash is at 0x00000 and the SRAM is at 0x80000
(512kB further), the linker will fail trying to create the signed 17-bit
relocation (it detect that it needs to truncate it)
Force the compiler to put another relocation as a workaround for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:24378
TEST=./util/make_all.sh ; make BOARD=it8380dev
check "version" and "gpioget" on spring, link and it8380dev.
Change-Id: Ife50adf3a26be28f113292f73a1a70e8d74b5d8c
Reviewed-on: https://chromium-review.googlesource.com/176913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Remove jumped_to_image check in system_run_image_copy because it's redundant.
disable_jump will be set by VbExEcDisableJump explicitly, whether the EC stays
in RO or jumps to RW.
TEST=Built and booted Peppy. Ran flashrom from user space and verified
the EC firmware was updated after reboot.
BRANCH=none
BUG=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: If1a3cf6158b3bc97c965298d2ab958b5fa7a5d7e
Reviewed-on: https://chromium-review.googlesource.com/172651
Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
BRANCH=none
BUG=chromium:318342
TEST=Run "ectool boardversion" on device with and without support
for board ID. Note, boards without support will return an error.
Signed-off-by: Dave Parker <dparker@chromium.org>
Change-Id: Ib7599570c84a7ed5cf70ce9d8336467785b35569
Reviewed-on: https://chromium-review.googlesource.com/176543
That way all the users of jump tags don't need to know about the
padding requirements.
BUG=chrome-os-partner:23851
BRANCH=none
TEST=enable CONFIG_CMD_JUMPTAGS, then 'jumptags'. Output should be
something like this:
20007fbc: 0x5550 UP.1 2
20007fc4: 0x4b42 KB.2 3
20007fcc: 0x4c50 LP.1 12
20007fdc: 0x4d54 MT.1 8
All the addresses in the first column should be word-aligned. The
sizes in the last column don't need to be a multiple of 4.
Change-Id: I91f9c29701a007ef8a56b5b7e0ea09930dfbea31
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175591
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add bug links, reword, or remove as applicable.
No code changes, just comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175326
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Remove comments if no longer applicable, or assign bug numbers if they
still are. Tidy some debug output. No code changes other than the
debug output.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms, pass unit tests
Change-Id: I2277e73fbf8cc93f3b1b35ee115e0f2f52eb8cf9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The common/ subdir was getting cluttered. Move drivers for external
components to a new driver/ tree, and move what used to be called
chipset_*.c to a new power/ directory.
This does not move/rename header files or CONFIG options. That will
be done in subsequent steps, since moving and modifying .c files in
the same CL is harder to review.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I67a3003dc8564783a320335cf0e9620a21982d5e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173601
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
Useful when debugging to determine if a user has an official build or
not, particularly early in the devel process where we're handing
builds to everyone. Particularly useful for proto1, since not all
those systems will be case-open servo-attached.
Also move get-version LPC command into system.c, where it's closer to
the system functions it calls (matches what we do for other host
commands).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Idb0f6edf31ca00e32f083be0b0d3f23ab79c5fba
Add build information (date/time/builder) which can be displayed at the
EC console.
Generate a version from the board name and the branch tag.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:27013
TEST=on BDS, run version command on the console.
inspect the built binary.
Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
When the flash base address is not zero (e.g. STM32L chip), the current
image index is wrongly computed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check it compiles for all boards, run on Discovery board and see
proper value.
Change-Id: I06f5508cdffce6d754bd93e870d64087d299c9c7
Preparatory work to introduce a second SoC : 3rd series 2/2
All the RO/A/B firmware copy code could be generic to all our platforms.
The console commands are a 'standard' API.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS EC console, check the reset cause with the 'sysinfo' command.
Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
