This fixes linker errors when the X86_POWER and/or POWERBTN tasks are disabled.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=remove X86POWER and POWERBTN tasks from ec.tasklist and make
Change-Id: I8a95020925e32ac4f80b9363f5aa6ab0a2d9ccd1
You can now enable/disable tasks more easily.
To conditionally compile a C file depending on the task FOO activation,
just write something like that in the build.mk file :
common-$(CONFIG_TASK_FOO)+=foo_source.o
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make all BOARD=link && make qemu-tests
Change-Id: I760fb248e1599d13190ccd937a68ef47da17b510
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7697
TEST=if it runs, it works
Change-Id: I36ab37a8cf1c3e4bf41bfb38e622e766cee8a4c4
When code is compiled for RAM (by re-enabling the flag in board.mk),
use the following openocd commands to load it:
reset halt
load_image ../../../build/link/ec.RO.flat 0x20000000 bin
reg 15 0x20000400
resume
Note that you'll also usually need to disable a bunch of modules to make
the code small enough to fit in RAM.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7681
TEST=if it runs, it works
Change-Id: I2b3cc69b361ad73706af3ff6de1ce952e8d5a0a9
Implement TPS2543 USB charging control.
It contains routine for setting each USB port as dedicated charging port
or standard downstream port. To allow us controlling the current
distributed to each port, we can select whether to allow 500mA or 1500mA
for each port.
BUG=chrome-os-partner:7476
TEST=Added USB port definition for BDS and tested GPIO output voltage
level is correct for all modes.
Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7456
TEST=if it runs, it works
Change-Id: Ib82afab7d53203af31eefc9887feb98679266ac1
For bringup, this powers on the x86 unconditionally.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
This just ensures the JTAG pins are reset to JTAG function on warm reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7448
TEST=none
Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7499
TEST=press and release power button; should see debug messages
Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
By default the scanning code would pull-low all column pins and listen to
any key press interrupt on input pins. This can save power compared to the
repeatly polling.
Once a key is pressed, the scanning code enters the busy loop and pull-low
column pins one by one. Then generate the scan code to host.
The code keeps polling after 1 second after no key is pressed. Then goes
back to interrupt mode.
BUG=none
TEST=Manual tested on S*y machine.
Change-Id: I0bf8877450dbd6ad1197a2fe1714ab755dc49a80
Implement EC lid switch interrupt handler and debouncing.
BUG=chrome-os-partner:7363
TEST=Manually test lid switch output signal is correct.
Use UART console to see debouncing is correct.
Change-Id: I74aad63330716da017fc4a57002349461c6a9b26
