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6 Commits

Author SHA1 Message Date
Simon Glass
bb27b96f13 cpu: Enable reporting of faults 
Faults should be enabled, otherwise we just get a hard fault whenever they
occur.

BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow; cause a fault and see that it is reported correctly
in the panic message, rather than just a hard fault.
Also tested on link, 'rw 1':

 > rw 1

=== EXCEPTION: 06 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000041 r2 :00000001 r3 :20003720
r4 :00000000 r5 :0000bbb4 r6 :2000371c r7 :00000002
r8 :00000000 r9 :20003721 r10:00000000 r11:00000000
r12:00000000 sp :200019a0 lr :00004ad1 pc :000054f6
Unaligned
mmfs = 01000000, shcsr = 00070008, hfsr = 00000000, dfsr = 00000000
Time:     0x00000000006f0938 us
Deadline: 0x00000000006ec3d4 ->   -0.017764 s from now
Active timers:
  Tsk  1  0x000000000072bc1e ->    0.242406
  Tsk  4  0x00000000006ec3d4 ->   -0.017764
  Tsk  5  0x00000000007a2333 ->    0.727547
  Tsk  6  0x00000000007a2193 ->    0.727131
  Tsk  7  0x00000000007a1fd9 ->    0.726689
  Tsk  9  0x0000000000eeb452 ->    8.366874
Task Ready Name         Events      Time (s)
   0 R << idle >>       00000000    6.854007
   1   WATCHDOG         00000000    0.000442
   2   VBOOTHASH        00000000    0.286203
   3   LIGHTBAR         00000000    0.018957
   4   POWERSTATE       00000000    0.020656
   5   TEMPSENSOR       00000000    0.000851
   6   THERMAL          00000000    0.000643
   7   PWM              00000000    0.000243
   8   TYPEMATIC        00000000    0.000015
   9   X86POWER         00000000    0.010582
  10   I8042CMD         00000000    0.000015
  11   HOSTCMD          00000000    0.000014
  12 R CONSOLE          00000000    0.000336
  13   POWERBTN         00000000    0.003883
  14   KEYSCAN          00000000    0.000297

Rebooting...

Change-Id: I95a4a7fae14359aa4e2b645d2110f91161e7df88
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26170
 2012-07-02 15:02:07 -07:00
Simon Glass
d5cb026142 Enable checking for divide by 0 and alignment faults 
These likely indicate errors, so we shold trap them. Possibly this
should be reconsidered for production.

BUG=chrome-os-partner:10148
TEST=manual:
build on all boards
build and boot on snow with a special rw command containing a division
by 0. See that it is trapped:
> rw 0

=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :08005eba r2 :00000000 r3 :20001048
r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8
r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002861 pc :0800368a
Divide by 0, Forced hard fault, Vector catch
mmfs = 02000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008

Turn off the cpu_init() setup, and see that it is ignored.

> rw 0
read 0x0 = 0x00000000
>

Similarly, try an unaligned access with the rw command with this enabled:

> rw 1

=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000041 r2 :00000001 r3 :200012ac
r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8
r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002861 pc :08003686
Unaligned, Forced hard fault, Vector catch
mmfs = 01000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008

but disabled it works:

> rw 1
read 0x1 = 0x5d200010
>

Change-Id: Id84f737301e467b3b56a7ac22790e55d672df7d8
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25410
Reviewed-by: Randall Spangler <rspangler@chromium.org>
 2012-06-21 06:01:22 -07:00
Simon Glass
004c607a96 Add an option to report panic fault information 
The fault status registers sometimes have useful information, so provide
an option to display these.

This adds about 1KB to the code size.

BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.

=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd
r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002
r8 :00000000 r9 :200013de r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a
Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000
mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008

Change-Id: I1a18c85ee63760502c92b300f5a87e57468469a5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24505
Reviewed-by: Randall Spangler <rspangler@chromium.org>
 2012-06-19 18:45:27 -07:00
Vincent Palatin
b4d996a5ea Move System Control Block registers to core header 
The SCB registers are defined in the ARMv7-M architecture, so they are
common to all chips.

We will need System Control Register (SCR aka SYSCTRL) to implement
power management on stm32.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=make BOARD=link && make BOARD=snow

Change-Id: I35c283731306541b3d21398c96fdca89954fe20a
Reviewed-on: https://gerrit.chromium.org/gerrit/25392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
 2012-06-15 13:18:40 -07:00
Randall Spangler
b2ac77b37b Support warm reboot from one EC image to another. 
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.

It's also used by factory EC update to update one image and then jump
to the updated image to finish the update.  In this case, the x86 does
NOT reboot.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:8449
TEST=manual

1) power on x86 and log in
2) sysjump a  --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted

Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
 2012-03-19 15:41:14 -07:00
Vincent Palatin
9a465855f8 NVIC registers are not SoC specific 
Preparatory work to introduce a second SoC : 5/5

All Cortex-M3/4 have the same NVIC registers at the same address.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=run EC firmware on BDS and check a few console commands

Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
 2012-01-25 22:50:07 +00:00