You can now add debug messages into a cts test and
they will be displayed with the test report html page.
The macro to use is CTS_DEBUG_PRINTF
Adding debug messages can potentially change test
results by slowing down the test, so you can choose
when compiling a test suite if you want the debug
messages present or not by adding --debug as an
argument when you call ./cts --build.
BRANCH=None
BUG=None
TEST=Manual
- Add a debug statement to a test
- Build the test suite with --debug specified
- Flash the boards
- Run './cts/cts.py -r'
- Open /tmp/cts_results/<board_name>/<test_suite>.html
to view see your debug message for the test
Change-Id: Icad8e0ac5cc905010caa4e7616f81572ce6ac771
Reviewed-on: https://chromium-review.googlesource.com/362475
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Remove repeated deadline resets. Deadline reset now in the STANDBY state.
Set radio frequency to match selected channel.
TEST=ble_hci_adv 0
BUG=None
BRANCH=None
Change-Id: Ic7ff0dba862c0216301d138413a89e4ef4a812fe
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367094
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There seems to be flaky issue where the nvmem tests don't fully
complete. I need to spend some time to try and understand the
mechanism. It doesn't happen on every build attempt and never
happens when I just run this particular test.
In the meantime, I don't want the builder to fail due to this
issue so I am removing this test from the test-list-host while
I debug the issue.
BUG=chrome-os-partner:55854
BRANCH=none
TEST=manual
Execute the command 'make runtests' in /platform/ec and verified that
the nvmem test is no longer executed.
Change-Id: I9f0778fd9fa17cf8949292f7abe8b05ccab2bae2
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367302
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If test suite doesn't finish or results are received
out of order, this is likely an indication of reset
or hang by one of the boards and all tests after the
point of corruption are marked as corrupted.
BRANCH=None
BUG=None
TEST=Manual
- Edit the gpio th code to change ordering of tests
or hang or reset, etc.
- Build and flash tests
- Run './cts/cts.py -r'
- You should see the results for all of the tests,
with all corrupted tests marked as corrupted
Change-Id: I7925e37db285a4e90e6e09bf3b187400ddfe9edf
Reviewed-on: https://chromium-review.googlesource.com/362614
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sometimes a perfectly sane image enters rolling reboot mode in case
some data change triggered a bug which prevents the normal startup and
causes a reset.
The most likely task causing in in case of cr50 would be the tpm task.
Let's add another check of the restart counter: should it reach the
value of 50, do not start the TPM task.
BRANCH=none
BUG=chrome-os-partner:55708
TEST=with this code plus an unaligned access introduced in tpm
initialization sequence in both RW_A and RW_B, program the full
image on the dev board.
Observe the device reset 50 time is rapid succession and then
stop with the following message on the console:
Bldr |511709
retry|50
Himg =4F992103..408D193E
Hfss =384E4655..EE13EBD0
Hinf =44D21600..B70529BD
jump @00044000
--- UART initialized after reboot ---
[Reset cause: rtc-alarm]
[Image: RW, cr50_v1.1.5044-8d6f7a2+ private-cr51:v0.0.68-633229c ...
+ cryptoc:v0.0.4-5319e83 2016-08-07 19:37:16 vbendeb@kvasha]
[0.004130 Inits done]
[0.006919 Active NVram partition set to 0]
Console is enabled; type HELP for help.
> system_rolling_reboot_suspected: roling reboots suspected. Try \
powercycling to clear
this condition.
[0.010502 Task 2 (TPM) exited!]
Change-Id: I6b08c5c1a02da9edf9bdf394e57cc56d2e595ad1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366892
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The nvmem space defined in the ec code base for the cr50 board is used
by the TPM2 library, which has its own nvram size definition. The two
definitions must match.
On top of the fact that the definitions are not locked to each other,
there is a third completely unrelated nvram size definition in
board/cr50/board.c.
This patch unifies nvmem size definitions between cr50 and tpm2
repositories by adding a compile time check for the size to be the
same on both sides.
Also, it turns out that two certificates (RSA and ECC) together do not
quite fit into the cr50 TPM nvram. Hence the total allocated nvmem
space is being increased to 20K (note that the actual nvram size
available to the TPM is less than half of this).
BRANCH=none
BUG=chrome-os-partner:55898
TEST=tpm does not lock up any more when 'tpm_client --own' is ran on the
Kevin-tpm2 command line
CQ-DEPEND=CL:367010
Change-Id: I20b4f54118bd2fa12e5bd5741d6c58fbe91f65d1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366796
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
While SPI routing on servo is not great, this is still fine
and asn't as painfully slow.
BUG=chromium:571477
TEST=flash some firmware
BRANCH=None
Change-Id: I26d67ed6cd1ba62a892388e96a21acc708265fc4
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366670
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Servo_micro sets usb config maxpower to 100mA.
Servo_v4 is set to self powered as it's powered by a
shared vbus and not be the bub it's connected to.
cr50 is self powered as no power is transmitted as part of CCD.
* Add CONFIG_USB_MAXPOWER_MA to define USB maximum power draw requested
per board.
* Add CONFIG_USB_SELF_POWERED to indicate that a device is not
powered by allocated USB power.
BUG=chromium:631302
TEST=lsusb reports 100mA bMaxPower (micro), Self powered (v4)
BRANCH=None
Change-Id: I79b8ce46f32d94f16104a4a8080104e30dce7f2c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363153
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When you run a test suite, cts will now save your
results for the suite/dut combo as a basic html page
BRANCH=None
BUG=None
TEST=Manual
- Connect dut, th
- Build/flash desired test suite
- Run './cts -r' to run tests
- Open /tmp/cts_results/<board_name>/<test_suite>.html
- You should see a table with test names/results
Change-Id: Id3de3bd7833be1bc5dde437c516db411aac47579
Reviewed-on: https://chromium-review.googlesource.com/362091
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added in classes for Board (parent), DeviceUnderTest,
and TestHarness. Reading, etc. should be easier now
BRANCH=None
BUG=None
TEST=Manual
- Build default
- Flash default
- Run
- Open /tmp/cts_results/nucleo-f072rb/gpio.html
- Should see a clean results page
Change-Id: Ide3f75281f0b5b8b40dabd36f8c239737dc527d6
Reviewed-on: https://chromium-review.googlesource.com/364236
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This change disables sleep only when a cable is actually detected.
Before it would disable sleep no matter what and if a debug cable was
not plugged in and then deteached then it would never enable it.
BUG=none
BRANCH=none
TEST=manual
update cr50
unplug suzyq
boot to kernel
verify cr50 is asleep
run 'powerd_dbus_suspend'
cr50 will wake up for like a second then go back to sleep
run 'apreset' on EC console
boot to kernel
verify cr50 is asleep
run 'powerd_dbus_suspend'
cr50 will wake up for like a second then go back to sleep
Change-Id: I8337f694853b7840ef932b38bd0fa6453d31cb3d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366861
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a case statement to handle HCI commands.
Add a test commands.
Try to match the hcitool syntax, so the same commands
can be executed on a Linux host.
Added lcmd (long cmd) to pass more parameters in fewer arguments
BUG=None
BRANCH=None
TEST=Use HCI commands to configure an advertiser and listen for
it using `hcitool lescan` on the host.
Change-Id: Ie28038847c9549eb1c27a605aa0fbad5efd3b2c7
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362145
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
I keep thinking this refers to "Embedded Controller" instead of
"Elliptic Curve Cryptography". Make it clearer.
There's no functional change, I'm just renaming a constant.
BUG=none
BRANCH=none
TEST=make buildall; run tests on Cr50 dev board
make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py
Change-Id: Iaf2e2839e88fdbbcb1a712934be56a0dd47e4a70
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366752
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Our UART interrupt must be able to preempt our SHI_CS interrupt,
otherwise console input may be lost. Adjust our relative IRQ priorities
to accommodate this.
BUG=chrome-os-partner:55920
BRANCH=None
TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from
the recovery screen, verify that all input is received by the EC.
Change-Id: I36203511f5883272287ac22d0704098fbd933758
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366622
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Add __keep attribute to irqprio entries to ensure they are not dropped
when CONFIG_LTO is enabled.
BUG=chrome-os-partner:55920
BRANCH=None
TEST=Manual on kevin. Check build/RO/ec.RO.map, verify that
.rodata.irqprio section is not empty.
Change-Id: I51ae23556d6f46b2cd7ba098f0e7a785292b2853
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366571
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
KSI2 get stuck when Refresh+Pwrbtn is used to reset EC,
so it was not able to detect the Esc key if it is also
pressed to enter recovery mode.
BUG=chrome-os-partner:55548
BRANCH=none
TEST=Reef EVT is able to enter recovery mode with Esc+Refresh+Pwrbtn
Change-Id: I0539e8fad9980cb563de94417079fe763c311887
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/366411
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously, the strapping configuration pins were only being
read following a POR reset event. In all other cases, the
strapping configuration was presumed to be stored in a long
life register. An issue with this method is that when Cr50
FW is upgraded (via Suzyq), there is no POR reset event until
either the battery becomes fully discharged, or the battery
is manually disconnected. Without a POR, following a FW upgrade,
the long life register will contain 0 and so neither the SPI
interface (on Kevin/Gru) or I2C interface (on Reef) will be
properly initialized.
Come to think of it, the contents of the scratch register should never
be zero unless this is a power on event, or a restart after migration
from the version not setting the scratch register.
Let's read the scratch register always if its contents are zero.
BRANCH=none
BUG=chrome-os-partner:50728
TEST=manual
Via the Cr50 console, cleared the long life register with
temp console command. Then executed a FW upgrade with Suzyq
and verified that the strapping pins are read and the correct
value is stored in the long life register. Note that 'reboot'
commands from either the Cr50 or EC console do not cause
a hard reboot.
Change-Id: I1b3aa92552b14bde9bda848aa3dc4c8221ce73a9
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366390
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The input should be active low, not active high.
BUG=chrome-os-partner:49959
BRANCH=none
TEST=manual
Remove and reattach the battery. "gpioget BATT_PRES_L" shows the
GPIO value changing appropriately.
Change-Id: I7d513471f6ab5e7e8cd0e601148915697fa9162a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366134
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
There are few reasons why the SoC may reboot which we haven't
been reporting (they just show up as "[Reset cause: other]").
This adds a bit of decoding to explain some of those "other"
reasons.
BUG=none
BRANCH=none
TEST=make buildall; try on Cr50
I tested one of the new reasons using "crash hang". It shows up
correctly as "{Reset cause: security]". I haven't specifically
tested all of the new reasons, but since this is basically just a
change to console message they should work too. I'll double-check
those cases once some blocking bugs are fixed.
Change-Id: I46daed29d7e37bda9034a3486127bed0ea25f803
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366400
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The crash command is used to intentionally invoke various failure
modes in a running system. This adds one more (and cleans up the
command slightly). The "crash hang" command does the same thing
as "crash watchdog", except that it disables interrupts first.
Some SoCs may require special handling to recover from that case.
BUG=none
BRANCH=none
TEST=make buildall; run on Cr50 hardware
Invoked all the options to the crash command, observed that the
appropriate response occurred in each case (a stack trace if
possible, followed by a reboot).
Change-Id: I18897cfc04726e6aeda59f4c6e742d7a0037cf80
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366127
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
This change fixes two issues. The first issue is that during rdd_init
debug_detect is set to the value of DEBUG_STATE_MAP. Debug_detect should
be the default map value of 0x420 which triggers an rdd interrupt when
cc1 and cc2 both have a value of 011 or 001. This will detect when a
debug cable is attached. ~debug_detect should detect when the cable is
detached.
The issue is after a soft reset DEBUG_STATE_MAP is not reset to the
default value so on the next rdd_init debug_detect was set to whatever
was DEBUG_STATE_MAP was last set to. If the debug cable is detected
before the soft reset then DEBUG_STATE_MAP will have a value of
~debug_detect and when rdd_init is called then debug_detect will be
initialized to that value of ~0x420. Now debug_detect does the opposite
of what we expect it to do. debug_detect detects when the cable is
detached and ~debug_detect detects when it is attached.
rdd_interrupt is called cr50 reads cc1 and cc2 and sees that a debug
accessory is attached so it sets DEBUG_STATE_MAP to ~debug_detect.
Because debug_detect does the opposite of what is expected then it will
trigger an interrupt when it detects a debug accessory. The debug
accessory is already attached so an interrupt is triggered. It reads cc1
and cc2 sees the debug_accessory attached resets the map to
~debug_detect. This cycle continues until the watchdog resets the
system. After this reset rdd_init reads the map to get debug_detect and
it is 0x420 because that is how it was last set and then rdd works
again.
This change fixes this issue by defining DEBUG_DETECT to be 0x420 and
not using the STATE_MAP value to do it.
It also looks like when the EC is off and we change the value of the
debug map, another RDD interrupt is triggered. Then it reads the debug
state and resets the map again another interrupt is triggered. It
continuously does this.
This change adds a check to see that the RDD was trying to detect the
state it currently senses before doing anything so the second interrupt
will be ignored.
BUG=chrome-os-partner:55793
BRANCH=none
TEST=manual
plug in a reworked suzyq
Flash the EC
verify a bunch of RDD interrupts aren't triggered and the
reworked suzyq can be used.
plug it in and out a couple of times to make sure everything
works.
Change-Id: I6f4e7b15cf9c53b965533df7fe23fae5b340f70d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364724
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This reverts commit 25f19f5bbd, which was
causing host command issues after sysjump. IBUFSTAT seems to behave
strangely. Additional investigation is required.
BUG=chrome-os-partner:55710,chrome-os-partner:55795
BRANCH=None
TEST=Verify host commands continue to work after sysjump.
Change-Id: Id94a9c4677bcae597b9353e081418e649e823564
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366173
Reviewed-by: Randall Spangler <rspangler@chromium.org>
when the daughter board is not connected, TCPC1 INT# (USB_C1_PD_INT_ODL)
will be floating since the external pull-up is located on the daughter
board as well, and this floating signal will cause an interrupt storm
and eventually cause a watchdog.
BUG=chrome-os-partner:55488
BRANCH=none
TEST=verify board no longer has watchdog reset when daughter baord
is not connected.
Change-Id: If1d73fa7d90f6ac52fd1ab0ac563a6bf5fd10dc0
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365499
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reef doesn't have the battery temperature sense pin connected to
the charger, hence reading the battery temperature from the battery
registers.
BUG=chrome-os-partner:55834
BRANCH=none
TEST=Using 'battery' & 'temps' console command verified,
temperature readings are same from both the commands.
Change-Id: I897e453296151f31344f3e0434202baa67c7025d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365970
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There is just one version of Cr50 firmware for all boards
that it's used on. However, on some boards the AP communicates
to the TPM via a SPI interface (i.e. Kevin) and on others, the
AP communicates via an I2C interface (i.e. Reef). In order to
dynamically discover which interface to configure, there are
strapping resistors added to the board which enables the Cr50
to detect which configuration to implement.
This CL is a first pass and is only looking at DIOA1 which is
pulled high for SPI and pulled low for I2C configurations.
The strapping resistor should be read when the AP is in reset
prior to it attempting to drive any of the lines used for
strapping. To ensure this condition is met, Cr50 will only
check the strapping options following a POR (power on reset).
Once the configuration type is discovered, a 'long_life'
register is used to hold the result so that the result can
always be available. The long_life register contents remain
unchanged until a subsequent power down event.
BRANCH=none
BUG=chrome-os-partner:50728
TEST=manual
Tested on Kevin and Reef. Verfifed by reading the stored value
that the SPI configuraiton is detected for Kevin and the I2C
interface is detected on Reef. In addition, verified on Kevin
that the Cr50 FW version is correctly reported to the AP which
means that TPM register reads via the slave SPI are functioning.
Change-Id: Ibd7624ad8e3b4126f6346dce0bc72f62a3cc6d18
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363014
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Watchdog events are delivered as internal ARM interrupts, so we
can print a crash dump and then reboot. However, if interrupts
are disabled when the watchdog triggers, it just hangs forever.
This CL configures the watchdog and processor lockup events to
trigger a hard reboot through a security alert. This is the only
way to make these events non-maskable.
BUG=chrome-os-partner:52597
BRANCH=none
TEST=manual
I added this console command:
static int command_hang(int argc, char **argv)
{
interrupt_disable();
while (1)
;
return EC_ERROR_UNKNOWN; /* Not reached */
}
DECLARE_CONSOLE_COMMAND(hang, command_hang, NULL, "Hang", NULL);
Without this CL, that command locked the SoC up until it was
reset from outside. With this CL, it reboots after a couple of
seconds.
Change-Id: I773c0138fd2243cdbcdd86b2c7138520155d7920
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365531
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
RADIO_STATE is broken: remove it.
Build on the geneneric radio support to send and receive
Bluetooth LE packets.
Add macros in registers.h to configure PCNF0 and PCNF1.
BUG=None
BRANCH=None
TEST=Send advertisements with console commands
ble_adv type length [interval_us]
for example: ble_adv 2 8
Advertisements should be received by other devices
The Bluetooth Address has the form C5:A4:A3:A2:A1:A*
The device name is a substring of ABCDEFGH...
ABCDEFGH @ C5:A4:A3:A2:A1:A2 (name length is 8, type is 2)
ABCDEFGH @ C5:A4:A3:A2:A1:A2 (name length is 8, type is 2)
ABCDEF @ C5:A4:A3:A2:A1:A6 (name length is 6, type is 6)
TEST=Listen for advertisements with console commands
ble_adv_scan chan [num] [addr0]
for example: ble_scan 37
Example output:
BLE packet @ 20000448: type 2, len 33,
5c.f3.70.6b.65.d2 AdvA
20000454: 02 01 08 17 09 43 68 72
2000045c: 6f 6d 65 62 6f 78 20 66
20000464: 6f 72 20 4d 65 65 74 69
2000046c: 6e 46 16
02 01 08 = 2 bytes, Flags, LE and BR capable
17 09 43... = 23 bytes, Name, "Chromebox for Meetings"
Change-Id: I2bd3f1d87acb069da0b56c1d7878e7d4fd6a06f3
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361960
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
This adds a hook that will run every second and complain if the EC
firmware was built for the wrong board.
BUG=chrome-os-partner:54947
BRANCH=none
TEST=tested on proto and EVT units
Change-Id: I9799249f74f3cea9a3f6b66b2441af8f16be7e01
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365505
Reviewed-by: Martin Roth <martinroth@chromium.org>
ESC+F3+Power+AC removal puts the battery into a soft-disconnect state
where is stops supplying current. Revive batteries in this state by
supplying a precharge current.
BUG=chrome-os-partner:55858
BRANCH=None
TEST=Manual on reef. Put battery into soft-disconnect state. Attach
charger and verify EC doesn't lose power and battery again supplies
current.
Change-Id: I9a772bf02a8bd40edc1db51de66de135f7299212
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365495
Commit-Ready: Rachel Nancollas <rachelsn@google.com>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Default to set DUT_CC1 to RD to enable USB and indicate
USB SS orientation. Add ADC entries for SBU detect.
BUG=chromium:571476
TEST=check that ADC maps to the right pins, check that usb3 initializes.
BRANCH=None
Change-Id: Ic9f7c6d1506b9ef83ed3b93a98516ab10b1a471c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364301
Reviewed-by: Todd Broch <tbroch@chromium.org>
Only report alert status if the PD chip is not being held in reset.
(idea borrowed from Amenia's implementation)
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: Ic637b1ab4e20527c806311a45c149b9ea5f64362
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360020
Reviewed-by: Martin Roth <martinroth@chromium.org>
Proto brought up 5V, 3.3V, and PMIC very early in the EC boot process
due to dependencies in the power topology. This had some other side-
effects, for example, a lot of the power rails would already be up by
the time the EC got around to processing the power state machine thus
leaving it waiting for signal changes that were supposed to come
later but had already occurred instead.
This patch updates the nominal codepath for rail and PMIC init on EVT
while using IS_PROTO to retain the Proto sequence if desired.
BUG=chrome-os-partner:54962
BRANCH=none
TEST=built and booted on proto and evt boards with subsequent patches
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: If9ddd41044f132e719b0b7f0ab80ed908ddb1d9b
Reviewed-on: https://chromium-review.googlesource.com/358913
Reviewed-by: Martin Roth <martinroth@chromium.org>
This removes write-protect ranges that are unnecessary so
that we save a bit of space.
BUG=chromium:633431
BRANCH=none
TEST=compiled only.
Change-Id: Ib34c6a125b001fc92a21f795ac3d922e77143342
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Print the reply bytes, be more consistent between %d and %x.
BUG=none
BRANCH=none
TEST=manual
Build debug version, verify that it prints more stuff.
Change-Id: I8c8a983360f4895ccc72b73ed67ce2d45a461bad
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365120
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
The kernel DP driver do not support hpd gpio detect, it use
EXTCON_DISP_DP cable state to decide power on/off DP PHY. Hence, do not
change GPIO_USB_DP_HPD level, but set or clear the TYPEC_MUX_DP when hpd
level changing in attention.
BUG=chrome-os-partner:52872
BRANCH=none
TEST=keep Type-C Dock inserted
1. plug HDMI cable, check with "ectool usbpdmuxinfo"
Port 0: USB DP
2. unplug HDMI cable, check with "ectool usbpdmuxinfo"
Port 0: USB
Change-Id: I369a92135bf0ca177e81eab6385980d51d863172
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/364401
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The chip revision and board version show up on the second line of
the returned string, immediately before the build info.
BRANCH=none
BUG=chrome-os-partner:55558
TEST=Queried version string using tpm_test
make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
RO_A:* 0.0.2/d0c9abe3 RO_B: 0.0.2/13eda43f RW_A: cr50_ [...]
B2:0 cr50_v1.1.5013-ab0e228+ [...]
^^^^
Change-Id: Iaa1efe5dca441aca24f281f76c1f218e24c844be
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365421
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Enable the SHI interrupt only after we have received and begun
processing our host command. Disable the SHI interrupt once our
transaction is complete (with either success or error status). This will
prevent the SHI interrupt from being asserted at the same time as the CS
interrupt, which can lead to the SHI interrupt being serviced first.
Also, it avoids needless, non-useful SHI interrupts during error
transactions.
BUG=chrome-os-partner:55710,chrome-os-partner:55795
BRANCH=None
TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached
(for host command spam), verify no errors encountered after 100 minutes.
Change-Id: I0ab20b0202ebcfe15c04b272ec67001a6a358dad
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364698
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Add functions to initialize and disable the radio.
Add packet definitions.
Update the spelling of the FICR_OVERRIDEEN register.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: I3a9e500d0f177b6ce77a3b6ed6a42acd4f49eb7e
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362175
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
