Dino Li
|
c2927f7dbb
|
cleanup: it83xx: pull pnpcfg_settings[] to the chip-level
With this change, we don't need to declare pnpcfg_settings[]
for each it83xx based board.
BUG=b:76022972
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1009544
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
2018-04-12 23:10:59 -07:00 |
|
Jett Rink
|
32bbdbf88c
|
bip: add initial power sequence usb-pd
BRANCH=none
BUG=b:75972988,b:76218141
TEST=buildall
Change-Id: I8d03f10828821c6d8e096d882db9f82cc901003a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/982562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
2018-04-09 15:18:52 -07:00 |
|
Jett Rink
|
aac3ae2983
|
bip: enable CONFIG_IT83XX_FLASH_CLOCK_48MHZ to support eSPI speed of 50Mhz
The FND clock must be greater than half the eSPI clock. Enabling this
option bumps the FND clock from 24Mhz to 48Mhz.
BRANCH=none
BUG=b:75972988
TEST=none
Change-Id: Ifbd82a5049c2cc88700100fda2b7cc0930425b91
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/978933
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
|
2018-03-26 14:41:20 -07:00 |
|
Jett Rink
|
cd17195b0f
|
bip: add UART interrupt to exit deep doze mode
Hook up UART RX pin to wake up ITE device when in deep doze mode.
BRANCH=none
BUG=b:76022415
TEST=none
Change-Id: Iabfd3ef51f9e63a6cbcca60fb916108528b0b294
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/978932
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
2018-03-26 14:41:20 -07:00 |
|
Jett Rink
|
d5a2d1fdf4
|
bip: remove GPIO_HIB_WAKE_HIGH option GPIO
GPIO_HIB_WAKE_HIGH is not needed or honored by ITE EC controller.
The lower power state on the ITE still honors the GPIO_INT_BOTH option.
BRANCH=none
BUG=none
TEST=none
Change-Id: I9aba6713c6e4773dd9473705ae020be9d4bac74c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/978871
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
|
2018-03-26 14:41:19 -07:00 |
|
Vijay Hiremath
|
3bd4e0de5e
|
Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
2018-03-24 07:32:29 -07:00 |
|
Jett Rink
|
a63f6a6240
|
bip: add gpio definitions
BRANCH=none
BUG=b:75972988
TEST=none
Change-Id: I4c20103083dc224d449bdc659a2b359808218cb0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/976526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
2018-03-23 14:51:06 -07:00 |
|
Jett Rink
|
7742e06e45
|
bip: initial add of bip skeleton
BRANCH=none
BUG=b:75972988
TEST=build all
Change-Id: Ibfadaee3b9584a7e2c87f6f607be4cba20f338b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/972142
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
2018-03-22 18:16:47 -07:00 |
|