Ensure that the short parameter '-p' works as well as the long one
'--progressbar'.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run 'stm32mon -p' and 'stm32mon --progress' none of them are
displaying the command usage.
Change-Id: If24accf0991dc9705a1fb3e29acf12581d7ab8dc
Reviewed-on: https://chromium-review.googlesource.com/952966
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Using only a Carriage Return as done to have a nice spinner is not
terribly compatible with logging the output of the tool to a file or
piping it to anything.
Add another option to have a simple progress-bar instead.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on Meowth, run flash_fp_mcu from the factory UI.
Change-Id: I0c37689d2ed1e45dff54b7f1eb2be515ea37e004
Reviewed-on: https://chromium-review.googlesource.com/936766
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Skip the empty blocks when writing even if they are in the middle of the
firmware.
This greatly improves flashing speed when the firmware contains a
signature at the end of the RW.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=./util/flash_ec --board=meowth_fp
Change-Id: I3cd1c1bd2670be23d3d9daf9b87d9af0bdfc8963
Reviewed-on: https://chromium-review.googlesource.com/880956
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Add a tweak to get faster flashing:
skip writing the empty trailing space at the end of the firmware image.
On the STM32H7x3, flashing 2MB of useless bytes over UART can be
really slow...
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=flash_ec --board=meowth_fp
Change-Id: Ie396ee7d5b5771e0f6249e38da37ef8329c84ae3
Reviewed-on: https://chromium-review.googlesource.com/856978
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On some chips, the full erase operation can take really long:
e.g 13s for 2MB mass-erase on the STM32H7x3 family.
Add a new mechanism retrying the ACK detection rather than extending
the default timeout which would imply very slow behavior in other cases
(e.g. connection).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=flash_ec --board=meowth_fp
Change-Id: I428f56341c31c327debb9a3d2eba9b12c768ba86
Reviewed-on: https://chromium-review.googlesource.com/856976
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On Goobuntu, the uapi copy of spidev.h doesnot contain
SPI_IOC_WR_MODE32, however the kernel supports the IOCTL.
To be able to build the tool outside of the ChromeOS chroot,
define it if it's not available.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
TEST=make buildall -j outside of the chroot
BUG=b:35567067
Change-Id: I04ec968e221c7d43f1bdb364a195d371370ec886
Reviewed-on: https://chromium-review.googlesource.com/614645
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add support for i2c boot protocol 1.1 and erase non-strech erase
command.
Add option to specify i2c slave address.
TEST=Read, Erase and Write SH on Ryu P4.
BUG=chrome-os-partner:36018
BRANCH=none
Change-Id: Ib0649323fd8879fef6e2dc5e62001c891afe128a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/250101
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Should be close to the STM32L476 in the STM32L4 family.
Slightly different flash/RAM.
It's currently running from the internal clock (HSI) at 16Mhz,
we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us
the PLL locking time).
The internal flash write/erase/protection is still not implemented for
the whole STM32L4 family.
Upgrade the SPI master support and verify that the TX works.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)
Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e
Reviewed-on: https://chromium-review.googlesource.com/442466
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Newer versions of glibc have moved to _DEFAULT_SOURCE and away from
_BSD_SOURCE. Trying to use the BSD define by itself leads to warnings
which causes build failures.
BRANCH=none
BUG=None
TEST=precq still works
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Change-Id: Ice24b84dc6a540695fc7b76e8f22a4c85c301976
Reviewed-on: https://chromium-review.googlesource.com/316730
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a command-line option to ask stm32mon to read the EC firmware image
to flash from the standard input when the filename is replaced by a "-".
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:398165 chromium:396233
TEST=use the following flashing commands:
cat build/fruitpie/ec.bin | ./util/flash_ec --board=fruitpie --image=-
./util/flash_ec --board=fruitpie
./util/flash_ec --board=fruitpie --image=build/fruitpie/ec.RO.flat
and check the content of the flash.
Change-Id: I8039ecb6910f912161a7f59c5f5e2fc80447ce7b
Reviewed-on: https://chromium-review.googlesource.com/220842
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This patch is base on new hardware board, veyron has not some stuff,
such as power led, charge en
BUG=None
TEST=Read log with servo board, it has reponse when type some commends
BRANCH=None
Change-Id: I45502fd1278f69db5e46fc9ab1deaee02fc8708f
Signed-off-by: zyw <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209231
Reviewed-by: Alexandru Stan <amstan@google.com>
Commit-Queue: Alexandru Stan <amstan@google.com>
Tested-by: Alexandru Stan <amstan@google.com>
Add STM32F03x as part of the STM32F0 family.
STM32F031 will be used for devices requiring low-end parts.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=along with the following CLs, run on STM32F051 Discovery with
limited RAM and Flash to mimic STM32F031.
Change-Id: Ie95303eaf00ce53fe7c8d2ac84c19a983aadbf0d
Reviewed-on: https://chromium-review.googlesource.com/189404
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Add support for the STM32F0xx family of devices using a Cortex-M0 core
and slightly newer peripherals than F1xx family.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board.
and pass all available unit-tests on target.
Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735
Reviewed-on: https://chromium-review.googlesource.com/188983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This make minor syntactic changes and renames some camel-cased symbols
to keep checkpatch from complaining. The goal is to reduce the
temptation to use 'repo upload --no-verify'.
This is a big furball of find/replace, but no functional changes.
BUG=chromium:322144
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180495
Add the ChipID for the stm32l152c board to stm32mon. Add discovery to the list
of supported boards in flash_ec.
BUG=None
TEST=With modified servo connector, see that image can be loaded onto
stm32l152c discovery board.
BRANCH=none
Change-Id: Ie16c64d17c907f7de765b09de98f534c486ae04c
Signed-off-by: Jeremy Thorpe <jeremyt@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170981
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
As we no longer have the low-tech dots to show the progression of the
on-going flashing, display a completion percentage to give the user a
hint of the ETA.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=./util/flash_ec --board=spring
and see accurate progression percentage reported.
Change-Id: I75ccbe3433acd6c94d03a08bf462ea4516e4ce02
Reviewed-on: https://gerrit.chromium.org/gerrit/42733
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change introduces the following modifications:
When used outside chroot on Goobuntu the serial interface fails to initialize
if parity enable bit is set (for a reason not clearly understood). On top of
that the tcsetattr() return value of zero is not a guarantee of success. To be
sure that the settings came through one is supposed to read back the driver
config and compare it with the desired config.
To add insult to injury, gPrecise driver rejects attempts to enable parity.
Parity setting is not essential in many cases, this is why we check the actual
config and if the only missing setting is parity we print a warning message
and continue.
In case an operation fails, the exit value should reflect that (so
that the autotest suite using the utility could report failure).
Often when the programming attempt is undertaken soon after reset,
this utility gets overwhelmed with the console output generated by the
EC on resets. Consume the output before proceeding.
Instead of printing a long set of dots (one per written/read block),
print a spinning wheel instead.
BRANCH=None
BUG=chrome-os-partner:15610
TEST=manual
. used the utility to program Snow EC both inside and outside
chroot, it succeeded.
Observed the failing attempt to set parity when running outside
chroot.
Observed spinning characters instead of stream of dots.
Change-Id: Id25595d35a2a3ca578639cebd508f599e618787c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/42310
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This updates the flash_size to match 128KB parts. Unfortunately
there does not seem to be an easy way to differentiate between the
64KB and 128KB parts at runtime.
BUG=none
TEST=tested on Snow
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ie1ca6f6d04753e91d937f67dec193fcf5566251e
Reviewed-on: https://gerrit.chromium.org/gerrit/26188
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
- throw away all the incoming garbage after a NACK to be protect against
unexpected behavior on the embedded monitor.
- increase the command timeout :
on STM32F100, I have measured up to 1.4s to execute the erase 64kB
command. With the current 2s timeout, it was failing when you are
unlucky (since it's using a integer second timestamp to measure the
timeout).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=with a Snow, flash the board using stm32mon -w ec.bin
from various states.
Change-Id: I260b3b1311eac9be7c43f835eeac68051befd24a
Reviewed-on: https://gerrit.chromium.org/gerrit/24314
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The STM32L15xx monitor does not implement the mass erase,
so we need to use the page erase feature and loop.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery, fill the flash with a pattern, then erase, write a
firmware image, read back the content of the flash, run the firmware.
Change-Id: Icf0e9812a5d491fea78472a0203ddbbc3e813b2f
When run with BOOT0=1 and BOOT1=0, the STM32L enters a system monitor
which allows flashing over the serial port (USART1 pins PA9 and PA10).
Implement commands to flash and run a program from a linux Host.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on a serial port connected to Discovery board pins PA9 and PA10,
run manually the various tools commands.
Change-Id: I42f95ed50a56d82d728989149b3e47210af9dc96
