Enabling the SPI slave interface and the host interface depending on the
detected PCH power state.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991
TEST=On Meowth, check that the MCU interrupt is seen on the CPU side and
we can still send host commands.
TEST=On ZerbleBarn, verify that the SPI slave interface is enabled at
startup.
Change-Id: Ie7b22e69178bc7d34be6ab28ab24db82fefd5a02
Reviewed-on: https://chromium-review.googlesource.com/966023
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Try to ensure the SPI host protocol byte codes (aka EC_SPI_xxx) are
transmitted and at the right time despite the errata and other brokenness
of the SPI HW controller in the STM32H7 rev Y silicon.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:73947203
TEST=on Meowth, run:
'while true; do ectool --name=cros_fp version || break ; done'
same thing with 'fpinfo', 'fptemplate', 'fpframe'.
Change-Id: Ia455dc0d4b2803a150122655460ef5c11afcda6c
Reviewed-on: https://chromium-review.googlesource.com/1012202
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, the base power was enabled when the base was detected by the
lid. However, we should only power the base when the AP is on since it
just wastes power otherwise. This commit adds a pair of chipset hooks
to kick the state machine on startup and disable it on shutdown.
BUG=None
BRANCH=None
TEST=Flash meowth, attach base with AP off, verify that base power is
not enabled.
TEST=Remove base and attach base, verify that base power is disabled
when removed and enabled when attached.
TEST=Shut AP down, verify that base power is disabled.
TEST=Remove base and attach base, verify that base power remains
disabled.
TEST=Power on AP with base detached, verify that base power remains off.
Change-Id: I4379789987dbe91c72d699c4d184b5c5cc812e5f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1020525
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
the latest schematics have been updated to reflect the I2C bus
numbering used in the chip datasheets. this updates the software to
be consistent with the new datasheets. this is only a renaming
exercise, there are no physical changes to the board.
BUG=b:75070158,b:78309559
BRANCH=none
TEST=it compiles
Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020721
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This patch makes the battery LED blink at 0.5 sec interval in white
when battery error is detected.
This patch also changes the pulse interval resolution from 1 sec to 100
msec. There is no functionality change.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:74940319
BRANCH=none
TEST=Verify pulsing and blinking are not affected. Verify battery LED
blinks as intended on Sona.
Change-Id: I0767a6004861b9f07bc846d2ba5bf0df9067a748
Reviewed-on: https://chromium-review.googlesource.com/1017305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The value of pwr_5v_en_req needs to be preserved when the EC performs a
sysjump, otherwise any task calling power_5v_enable(tid, 0) will drop
the 5v rail for the entire system.
I've scheduled this at HOOK_PRIO_FIRST for restoring the value to ensure
that no other init hooks read a stale value, but I'm not sure if that's
necessary.
BUG=b:78275296
BRANCH=none
TEST=Booted yorp with power only connected to USB-C port 0
Change-Id: I3a9ed24a5fde02b60163ad2c5e3252759f8c1c5b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020066
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Add CONFIG_MKBP_EVENT and CONFIG_MKBP_USE_HOST_EVENT
to send sensor events to AP.
BUG=b:77342604
BRANCH=none
TEST=view sensors in AIDA64 Android app in ARC++
Change-Id: I3687072903d251bccb2cdf7670b0780a906dd22d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1012457
In order to ensure that all chipset init/shutdown operations happen
within the context of chipset task for APL/GLK:
1. Update chipset_force_shutdown to only set a flag force_shutdown to
indicate that chipset shutdown is requested and wake the chipset task.
2. Make chipset task (within the power state machine) call
internal_chipset_shutdown.
3. Make internal_chipset_shutdown reset force_shutdown flag and make a
callback to weak function chipset_do_shutdown to trigger chipset
shutdown.
BUG=b:78259506
BRANCH=None
TEST=Verified that "apshutdown" on EC console results in chipset
shutdown action being taken within chipset task.
Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018737
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Now that all boards are moved to using chipset_pre_init_callback,
get rid of hook notification for CHIPSET_PRE_INIT from x86 power state
machine.
BUG=b:78259506
BRANCH=None
TEST=Verified that yorp still boots.
Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018736
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This change adds a callback for chipset_pre_init_callback which is
made by x86 common power state machine when in G3S5 state. Until now,
there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by
chipset task when in G3S5 state. However, there are at least following
reasons why this should be a callback and not a hook notification:
1. The initialization that is done as part of pre-init could be
essential for the power state machine to make progress. Though the
chipset task goes to sleep waiting for power signals after the hook
notification, pre-initialization can all be done as part of a callback
since it is mostly board-specific code that is doing work to
initialize PMIC.
2. Typically, boards use I2C transactions to setup PMIC on getting
chipset pre-init notification. However, since i2c transfers are not
encouraged in hook task, they have to be deferred anyways.
3. Since the initialization is being done as part of hook task, use of
any constructs e.g. pwr_5v_en_req which allows multiple consumers to
enable/disable power rails will use task id for hook task. Instead it
is better to provide correct information about the task by letting
chipset task perform this request.
Thus, this change adds a callback chipset_pre_init_callback in G3S5
state for x86 power state machine. This callback is guarded by
CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK.
The hook notification is left as is for now until all x86 boards are
moved over to using the newly added callback.
BUG=b:78259506
BRANCH=None
TEST=None
Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018733
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Now that board version can come from CBI, we can have a real error
reading it. We should pass that error to the console or to the
AP on the host command and let the AP firmware (or user) decided how to
handle that error case
Also update the CONFIG_BOARD_VERSION to be derived instead of needed
in most cases.
BRANCH=none
BUG=b:77972120
TEST=Error reported on EC console and AP console when CBI is
invalid on yorp
Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1015776
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Cr50 RMA Open will disable write protect. Make sure it is disabled. If
it isn't, manually disable write protect after rma_auth. If cr50 reboots
or loses write protect, cr50_rma_open can now be used to force disable
it again with cr50_rma_open -w.
BUG=none
BRANCH=none
TEST=none
Change-Id: I096cff51ae20b8a4cfbfa92892a011ff48f4cc49
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1016023
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Without this, we see this line when running flash_ec.
util/flash_ec: line 787: [: =~: binary operator expected
These kind of tests require double brackets.
BUG=b:77825616
BRANCH=none
TEST=run util/flash_ec using servo_micro on staff.
Change-Id: I6baecec2252276ac06992fd2b2e50f74d55805f2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1018560
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Since the proper signer utility has been introduced in the chroot,
there is no need in generating reduced command option set when
building a self signed image.
Also, the same manifest can be used for all images, self signed or
signed using a fob. The manifest needs to be tweaked for the self
signed images to match the test Key ID.
Since the same base manifest is used for all signings, there is no
need to support the "poor man's json parser" any more.
Rearranged build.mk to accommodate new logic, and added some comments.
BRANCH=cr50, cr50-mp
BUG=b:78212718
TEST=verified that images with proper header version are created when
both self signed and signed with a private key coming from the
signing fob.
Change-Id: I5a1f8a223098b0a6c830ef24ffe380fc0badcafa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1017238
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
After a successfully PD packet transmit, a PD_EVENT_RX is issued
which could trigger a premature reading of a PD Packet before
the entire packet is received.
BUG=b:71620429
BRANCH=NONE
TEST=manual
Tested on Scarlet with the following three dongles:
ASUS 3-1, (HDMI, USB, TYPEC): Tested with USB-Keyboard, TypeC power
adapter, and HP monitor.
Cable Matter 6-1, (DP, HDMI, USB, SVGA, ETHERNET, TYPEC): Tested with
USB-Keyboard, TypeC power adapter, Ethernet and HP monitor
(DP and HDMI). SVGA was not tested.
Cable Matters 6-1, (DP, DP, USB, USB, ETHERNET, TYPEC): Tested with
USB-Keyboard, USB-Mouse, Ethernet, and two HP monitors
(Scarlet was mirrored on both monitors)
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: Ib07182201d954cf4b9616277f9c14bbbb337197e
Reviewed-on: https://chromium-review.googlesource.com/1015417
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Nami/Vayne uses a dual color LED to show power/charge status as follows:
Charging Amber on (S0/S3/S5)
Charging (full) White on (S0/S3/S5)
Discharge in S0 White on
Discharge in S3/S0ix Pulsing (rising for 2 sec , falling for 2 sec)
Discharge in S5 Off
Battery Error Amber on 1sec off 1sec
Sona - Battery LED (dual color)
AC is attached Solid ON White
charging Solid ON Amber
Discharge in S0 Off
Battery Error Blinking white (0.5 sec On and 0.5 sec Off)
Discharge in S3 Blinking white (1 sec On, 1 sec off regardless AC status)
fuel < 10% Blinking white (1 sec On, 1 sec Off)
Sona - Power LED (single color)
System S0 Soliid On
System S3 1 second on, 1 second off
System S4/S5 Off
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:74940319,b:77941051,b:73999799
BRANCH=none
TEST=Verify LED behaviors in S3, S0, charge, discharge on Nami and Sona
Change-Id: I55b40742135a49f48044f561eb2dbd82b5556d07
Reviewed-on: https://chromium-review.googlesource.com/1011293
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ec3po writes to the user pty, which may or may not be open.
Since ptys have limited buffer space, we need to avoid
writing to them if they will never be drained.
ec3po now looks for HUP to indicate whether the pts is opened
or closed, and reads/writes accordingly.
BRANCH=None
BUG=b:76111225
TEST=dut-control ec_board:fizz x 400
Change-Id: Icbecb2e42b261659a006eb1b9fc6dd73490a2218
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1014792
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit adds an optional console command that will dump the contents
of the battery charger IC registers. Currently, the only chargers
supported are the BD9995x as well as the ISL923x.
BUG=None
BRANCH=None
TEST=Enable on meowth; Flash; Verify that the command works without any
issues.
Change-Id: I2221efe0ed6e0f6063c97547e0da2d775bf4da45
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1016004
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
NPCX79nxB chips add UART FIFO support with 16-bytes of TX/RX buffers.
This CL enables the UART FIFO mode when NPCX79nxB chips are used.
The UART interrupt priority is decreased from 1 to 4 because now it has
the capability to buffter data in the FIFO when ec is serving the
interrupts with higher priority.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=stress test the uart port by shell command "while true; do echo
'taskinfo'>/dev/pts/19; sleep 0.1; done".
Change-Id: Ib09c1b5550d0db249201fc4fdd8d3b28c24b8a8e
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1012002
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the FLPRG# strap pin is set to active low, and npcx7 chip is reset,
it will enter uut mode. This CL adds the host tool to communicate with
npcx chip in uut mode to flash ec firmware via UART port.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=
------------------------------------------------------------------------
1. Connect the servo connector (J24) on npcx7 EVB to servo board v2 via
flex cable.
2. Manually turn the switch SW1.6 to "ON" on npcx7 EVB.
3. Reset ec by issuing Power-Up or VCC1_RST reset.
4. Manually turn the switch SW1.6 to "OFF" on npcx7 EVB.
5. Move npcx7_evb from array BOARDS_NPCX_7M7X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. "./util/flash_ec --board=npcx7_evb."
Change-Id: I2c588418e809e59f97ef4c3ad7ad13a3fef42f11
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/952037
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: Alexandru M Stan <amstan@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The initial I2C operating speed of the port-0 TCPC chip is 400kHz.
It requires changing a register addr:0x48 to a value 0x03 to increase
its speed to 1MHz.
The BC1.2 chips on port-0 and port-1 also operate at 400kHz, according
to the datasheet.
So lower the I2C speeds on two TCPC buses to 400kHz.
BRANCH=none
BUG=b:78142256
TEST=Use console to enable TPCP power and check I2C communication:
> gpioset EN_USB_C0_TCPC_PWR 1
> gpioset USB_C0_PD_RST_R_L 1
> i2cscan 1
Scanning 1 tcpc0......................................
0x4a...
0x50........................
0x80...............................................................
> i2cxfer r 1 0x50 0x00
0xaa [170]
Change-Id: I665136d738de50db8beeed338e3102fb5ca6fc84
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1015763
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
After using joint 5V rail code (CONFIG_POWER_PP5000_CONTROL) we cannot
wait for the 5V rail to go down because another task may be using it.
BRANCH=none
BUG=b:78188213
TEST=apshutdown on yorp no longer watchdog resets
Change-Id: Ibc7e3eb2f7b3271fccd6ef0d92cce156c20bd688
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1015845
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add initial support, like UART, GPIO, I2C, buttons, etc.
Add some hacks for early bring-up.
BRANCH=none
BUG=b:74395451
TEST=BOARD=cheza make
TEST=Flashed the EC image to cheza. Verified AP power-on, booting
coreboot/depthcharge with UART, and then booting kernel from USB.
Change-Id: Id057abb491553bbffd3c57a6f48187ac2f2ff9a6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969420
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
The BQ24392 driver controls power on the PP5000_A rail so that BC1.2
detection can be performed when the AP is off. However, that rail is
also controlled by the chipset task, so CONFIG_POWER_PP5000_CONTROL
needs to be defined to keep 5V rail up when necessary.
Calls to power_5v_enable() must only be done when the build has a
chipset task (otherwise, that function is not defined).
BRANCH=none
BUG=b:77874283
TEST=Booted Yorp with software sync enabled
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: Ib75655944aa05e381da922da8e916dc5d4dd9f85
Reviewed-on: https://chromium-review.googlesource.com/1014397
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
flashrom --get-size seems to return a size of 0 in some failure cases.
add specific handling of this case so we don't proceed and end up
failing with a somewhat misleading message like:
Error: Image size doesn't match: stat 524288 bytes, wanted 1048576!
BUG=none
BRANCH=none
TEST=flashrom now fails with "chip size is 0" instead of complaining
about wanting a 1048576 byte image.
Change-Id: Iab4d0843d86ceec9f0ca482d9e060a33c7a58c7a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1011823
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
rk3399 systems need terminations on the SPI signals in S3 and all other
low power states. Add support for enabling the pulldowns and pullups on
the correct pins.
With this change, if BOARD_NEEDS_S3_TERM is set in the board properties,
cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown
on all of the SPS signals. To keep the pulldowns from interfering with
the sps peripheral, s3_term will also disable the input for those
signals.
BUG=b:62200096
BRANCH=cr50
TEST=Flash onto bob. Make sure cr50 enables and disables terminations
when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do
anything.
Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/991338
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The problem here is that both normal detection range (120-300mV)
and reverse connection detection range (450-500mV) are on the same
side of the interrupt pin TTL level.
So if we accidentally sample the ADC at the wrong time (either on
connection, or after a side-band wake signal from base), we may
fall into a trap where we assume that the base is connected in
reverse, while the value may just be a transient.
We have seen this case in the field, due to side-band wake pulse
from base EC, but this could potentially happen on attach as well.
The code debounces the reverse detection signal a little longer
(this has no impact as the base is not functional anyway), so that
we only consider that the base is connected in reverse if the ADC
value is within the range twice in a row.
BRANCH=poppy
BUG=b:77828249
TEST=With HACK CL to emulate bug:
- Press a few keys, hammer gets disconnected
- Connect/disconnect hammer a few times, sometimes it does not
get disconnected.
TEST=Base connection, normal and reverse, still works properly.
Change-Id: I2ccb911472dd591146e3b0e68400c8bd55368dba
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1010044
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-toggling is currently disabled due to b/77544959.
BUG=b:73793947
CQ-DEPEND=CL:988414
BRANCH=none
TEST=Boot Nami. Verify PD power is negotiated and bettery is charged
with a Zinger through the Analogix port.
Change-Id: Ie817883027eb8623a8115aa8194fe4df50c3ce72
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969989
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Replace ADC-based board version with CBI/EEPROM board version. This will
cause all of the existing boards to report -1 (or 65535) as their
board version until you can update it from the kernel.
To set your board version to 0 run the following command in
the AP console when WP if off (e.g. battery removed)
$ ectool cbi set 0 0 1 2
BRANCH=none
BUG=b:77551185,b:77900842
TEST=wrote to cbi from ap console and verify flash state on
ap and ec console
Change-Id: I03987cc89ca4c14580dcf61de23780fe5304663b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1008832
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently we only support the Acer LG and Panasonic battery. There is
a 3rd Acer battery type that Quanta could be providing us with for
Yorp proto boards. This CL adds support for the Sanyo battery.
BUG=b:74132235
BRANCH=none
TEST=verifed that when connected to Sanyo battery that the battery is
reported as present.
Change-Id: I1810da59866795e93340163216412441be098795
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1011557
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL adds support to check if the OCM flash is erased and if not,
will erase it at initialization time. These changes are encapsulated
in a new config option CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE and this
option is enabled for Yorp boards.
BUG=b:77658388
BRANCH=NONE
TEST=make -j buildall. Tested on a board that hadn't yet been
erased. Verifed the message
"anx7447: OCM flash checked and successfully erased"
was in the EC log, but did not show up on subsequent reboots.
Change-Id: I660e76a9498d3dc1ba821a04317b324f716c5089
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/988414
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Also updated the description of the cbi command in help
BRANCH=none
BUG=none
TEST=wrote directly to flash and verified the cbi command updated
Change-Id: I54b5d995a0f06b9566622a5079da11ce575fb309
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1008831
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
