When deciding which of the two images to start, A or B - consider the
image timestamp if everything else is equal. The later image should
take precedence.
Also, simplify the existing logic, and consider image A to be 'newer'
if both copies are the same otherwise.
BRANCH=none
BUG=chrome-os-partner:37754
TEST=with the rest of the patches applied, verified that the newer
image of the two gets started
Change-Id: I2c7a50ecfc8d254498c8e96f8651b8d53005897c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327414
Reviewed-by: Marius Schilder <mschilder@chromium.org>
The launcher should explicitly disable writes to the code space where
the loaded code is going to be running from.
BRANCH=None
BUG=chrome-os-partner:37554
TEST=with the rest of the patches applied firmware updates work as
expected.
Change-Id: I744f7016e4427188f53e8fa3302e8c06cf836e2e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327413
Reviewed-by: Marius Schilder <mschilder@chromium.org>
We found the deviation of ITIM32 is huge since apb2's clock isn't divisible
by 1MHz. (The default resolution of hwtimer is 1us.)
The solution is set the freq of apb2 the same as core clock. Note apb2 is
twice value of original one. It will increase power consumption slightly.
But we found the difference is acceptable no matter core clock is 15M
or 13MHz.
In this version, we also use the arrays to adjust i2c bus timing if
bus' freq is 400K or 1MHz for all source clock freqs of i2c.
Modified sources:
1. i2c.c: Support all source clock freqs of i2c for best bus timing.
2. clock.c: Set divider of apb2 if it's clock isn't divisible by 1MHz.
3. uart.c: Modified baud-rate for apb2 which is the same as core clock.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I6089caaaf9aa16186d7c6acf6f5fea0682a55655
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/327120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fixed the bug that some of DP80's data is skipping if the speed of writing
by host is high. The solution is grabbing all data and sending them to UART
until FIFO of DP80 is empty in ISR.
Modified sources:
1. lpc.c: Fixed the bug that some of DP80's data is skipping.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie53a5c7f0a80a1f836b571a00871cb57b42c87db
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/326931
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The output enable bit was being set before the output value was
initialized.
BRANCH=none
BUG=none
TEST=Confirmed the fix with a logic analyzer
Change-Id: If8228d716b4924b5fd65b8f59436f4b37f05644e
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327212
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The required output length is not known until padding
verification completes (this check is already done
in the appropriate padding check functions).
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2/ pass.
Change-Id: I452244d052b7f334a6907bd653645671033a0890
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/327074
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the
wake masks when the SMI is invoked. For S0ix, EC sets and clears the
wake mask via this patch.
These functions are directly invoked from the state machine transition states.
During S0ix entry, the wake mask for lid open is enabled. During S0ix exit,
the wake mask for lid open is cleared. All pending events are also cleared
BRANCH=none
BUG=chrome-os-partner:48834
TEST=test lidopen in S0ix
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f
Reviewed-on: https://chromium-review.googlesource.com/320190
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If a label is specified, then the NUL terminating
character is considered part of the label per the
TPM2 implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2/ pass.
Change-Id: If5fccc293f7ab52fd6c33e2f3c38695c2921d919
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/326910
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
In normal operation the 16 bit timer number 1 is set up to count every
microsecond, and every 1000 counts (i.e. every millisecond) to assert an
IRQ (Interrupt Request). After a microsecond the IRQ is deasserted.when
the count is again not at its limit.
The IRQ handler ignores the IRQ from the timer itself.
If the clock is stopped or the autoreload of the counter is disabled
then the value of the count is left unchanged. If this count is the
limit then the IRQ will remain asserted. For stopping the clock this is
approximatly a 1 in 1000 chance, or is certain if the autoreload is
disabled.
If the IRQ from the timer continues to be asserted, then the NVIC will
continue to generate a fresh call to the IRQ handler as each previous
exception completes.
The fix is to do what almost every IRQ handler does for almost every
processor, and clear the request in the peripheral that is causing the
interrupt, rather than hoping that the timer will clear it itself. This
agrees with how the event timer is used. There may be a lurking bug in
the system timer handler as well as it also expects the timer to clear
its own IRQ.
BUG=chrome-os-partner:48499
TEST=Pass 2000s of continuous calls to port_80_interrupt_disable() /
port_80_interrupt_enable() without WDT being triggered. Stop the
autoreload and see it doesn't watchdog.
BRANCH=glados
Change-Id: I4726854b7784e2e4a39b8cb74c350206d71f90df
Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/326781
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Referring to i2c ports as i2c0 thru i2c4 is confusing, due to the
special naming of controller 0 ports, so use their actual names from the
datasheet.
BUG=None
TEST=Trigger failure on i2c0_1, verify that "i2c0_1 bad status .." is
seen on console.
BRANCH=glados, strago
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibd0d638e5af1c0a64e6f4b1a709b790b6b10d5e6
Reviewed-on: https://chromium-review.googlesource.com/325822
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
EC boot / hash computing can be a bottleneck for system boot time.
Reduce this bottleneck by running our processor at 48 MHz through boot,
until vboot hashing of RW completes.
BUG=chrome-os-partner:49583
TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and
'cbmem' delta between 'vboot select&load kernel' and 'finished EC
verification' is reduced to ~250 ms (which includes sysjump time).
BRANCH=glados
Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326792
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The new register definitions file has been supplied, it is not
defining some fields which were present only in FPGA. Some tweaks are
required to accommodate this.
BRANCH=none
BUG=chrome-os-partner:50141
TEST=new code successfully boots on the evaluation board
Change-Id: Ie4158554e0aaf039d59669558861a763a23f0ceb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326803
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The TPM2 api does not require keys to be word-aligned,
so have the compiler generate alignment-safe reads where
necessary.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2/ pass, more TCG tests pass.
Change-Id: I247e29f2bec139ab7ed4010ffb58cdae77ba9e0b
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/326201
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Creating bootloader for the chip involves signing the image with an
'air gap' - some physical presence action is required. We don't want
this to be required when the builder is building cr50 for test
purposes.
The solution is to keep using the dummy private key when building by
default, and invoking make differently when building an image which
would be accepted by the hardware.
Setting CR50_RO_KEY variable in the environment or in the make command
line will cause the signer use the value of this variable as the name
of the file containing the key to use for signing the RO image.
Should this file be a public key, the signer will stop and look for a
fob containing the matching private key, and will stream the RO image
through the fob for signing.
Using the fob requires that the signer runs under sudo, but we do not
want the generated files to belong to root, some more code is added to
change the generated files' ownership to user running the make.
BRANCH=none
BUG=chrome-os-partner:49950
TEST=ran the following tests:
- verified that the build still succeeds by default.
- invoked make as follows:
CR50_RO_KEY=cr50_rom0-dev-blsign.pem.pub make BOARD=cr50
observed the signer stop to wait for the user to interact with the
USB fob and proceed. Made sure that the generated image runs
successfully on the evaluation board.
- verified that 'make BOARD=cr50 clean' still works (i.e. none of the
generated files is owned by root).
Change-Id: I733ec6386c1dfd838d83d22fb589fa64e5eeaced
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326484
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
With transitioning to silicon there is no need to check if the
hardware includes USB subsystem or not.
BRANCH=none
BUG=chrome-os-partner:50141
TEST=the cr50 image successfully boots to the ec prompt
Change-Id: I593205cf307e0fce5e74ea695ed1cf5bfea8fde4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326482
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To get better power consumption in S0, we add FW support for
CONFIG_LOW_POWER_S0.
Before entering deep idle in S0, we must enable Host interrupt to wake up
EC if it needs to service LPC bus.
This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h
to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of
PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of
PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal.
In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR
since preload counter is changed by __hw_clock_source_set all the time.
We also found there're no event set if it's deadline is over 32 bits but
current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if
ITIM32 expires, FW set an event for ITIM32 after process_timers().
Modified sources:
1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition.
2. clock.c: Enable Host interrupt for LPC.
3. clock.c: Disable LP_WK_CTL for better power consumption.
4. gpio.c: Add ISR for Host interrupt.
5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed.
6. register.h: Add uart_clear_pending_wakeup function.
7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow.
8. fan.c: Enable deep sleep if duty cycle is zero.
9. include/system.h: Add SLEEP_MASK_FAN for fan control loop.
10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the
instruction pipeline.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/324651
Reviewed-by: Shawn N <shawnn@chromium.org>
The max retry counts are based on the TSMC specification. This is a necessary
change given that we're using their smart program/erase algorithms.
BRANCH=none
BUG=chrome-os-partner:45366
TEST=Tested RW updates.
Change-Id: I18ca09e54ce13f2cf75dac32fb2457d5963ca040
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/325535
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch introduces HOST_CPPFLAGS to be used for all
objects being compiled with HOSTCC rather then the target
compiler.
Since glibc is not linked into the EC, no glibc include files
should be included in the EC code base. Hence, create local
definitions for clock_t and wchar_t that match what the glibc
include would have done, and remove some unneeded includes.
Due to very eager optimization, we have to give gcc a little
notch to not kick out memset.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=chrome-os-partner:43025
BUG=chrome-os-partner:49517
BRANCH=none
TEST=compile tested
Change-Id: Idf3a2881fa8352756b0927b09c6a97473358f239
Reviewed-on: https://chromium-review.googlesource.com/322435
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There is probability to fail in firmware_ECWatchdog FAFT test by using
CONFIG_WATCHDOG_PERIOD_MS period for check timer. Use
CONFIG_AUX_TIMER_PERIOD_MS instead can fix it.
Modified drivers:
1. watchdog.c: change watchdog check timer period from
CONFIG_WATCHDOG_PERIOD_MS to CONFIG_AUX_TIMER_PERIOD_MS.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I93e700968751ecd58f032c2f5866cf4f2eb0ffe4
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/324712
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The makefile is missing an explicit dependency which ensures that the
signer utility is available by the time the RW_B image is built. This
works most of the time, but once in a while RW_B gets ahead in the
race and the build fails.
Adding explicit dependency will prevent this from happening.
BRANCH=none
BUG=chromium:578761
TEST=make buildall -j still succeeds.
Change-Id: I7f5223f51e71b1d78de012bf5d934f1a17c86cc0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/325031
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Allow boards to take action (such as entering a custom low-power
hibernate-like state) before putting the chip into hibernate state.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual with subsequent commit on chell. Verify board-level
hibernate callback is called when "hibernate" is run on EC console.
Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324086
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The implementation for sha256_hash() copied
and incorrect number of bytes to the output.
This change provides a fix and a test.
TEST=added test case
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I74e98c6f5005a14dd5c0ca19ea7540622dd6c7d7
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324391
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Adds the the code necessary to support muxed inout peripherals on
cr50 like SPS and SPI0 by adding a new signnal to pin connection
flag. Note these are for direct wired peripherals where no muxing
is necessary, the input pads just need to be enabled.
BRANCH=none
BUG=none
TEST=verified pinmux registers through m3
Change-Id: I1a375a3a14fb44fc4f9ced764fd2c54bb2b91e22
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323848
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
of the two RW images if set.
Imported the Haven "signed_header.h" file into chip/g and fixed prior
references to the util/ copy.
BUG=none
BRANCH=none
TEST=Went through a full update. Simulated a botched update.
Change-Id: I1e4c006ef391270a7e350fea6f43cc1a1b057d0e
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324109
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We have a limitation for EC interrupt vector registers.
System may read incorrect interrupt number in ISR so we need to add
a workaround to prevent it.
The following is a example that got incorrect interrupt number:
1. REG IVCTx = 0x10. (no interrupt pending)
2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt of same interrupt group occurs
(for example: INT134, IVCTx = 0x96) while the system is reading the
interrupt vector register for EC INT6, we may end up with an incorrect
interrupt number between 0x16 and 0x96.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart,
LPC, I2C, and PECI.
2. Console command 'taskinfo'.
Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17
Reviewed-on: https://chromium-review.googlesource.com/322097
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit updates the cr50 watchdog and hwtimer drivers to use the
hardware header specified regdefs to determine the frequencies for
the cr50 device.
BRANCH=None
TEST=Verified gettime and watchdog behavior on cr51
BUG=chrome-os-partner:46737
Change-Id: Iec7dc56b160dbec1b71077cecfd5561436d6f3ab
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321867
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
After talking with Simon Glass about this we concluded that this was an
optimization that is not needed, as such, and since it is only used in
one location and only available from one chip family I'm removing it.
This further simplifies the GPIO API and removes more uses of port/mask
pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a
Reviewed-on: https://chromium-review.googlesource.com/323827
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new gpio_reset function simplifies the pattern used in this code,
that of returning a GPIO to its original configured state. It also
removes a few instances of using port/mask pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d
Reviewed-on: https://chromium-review.googlesource.com/324059
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In rare case, executing i2c_interrupt function will generate unnecessary
START condition if START bit is 1 in SMBCTL1.
Please see the layout of SMBCTL1 register below.
Bit [7] - STASTRE
Bit [6] - NMINTE
Bit [5] - GCMEN
Bit [4] - ACK
Bit [3] - EOBINTE
Bit [2] - INTEN
Bit [1] - STOP
Bit [0] - START
In order to set or clear bits of INTEN and NMINTE, we need to read SMBCTL1,
or the bit2,6 and write back to register. But we will issue unnecessary
START condition if bit 0 is 1. (ie. Start condition is not sent yet)
Then FW will receive unexpected SDAST interrupt and sometime it collapses
state machine when i2c receives NACK condition.
The solution is enabling these two bits in i2c_init_bus function. Using
task_enalble/disable_irq (NVIC register) to enable or disable i2c interrupts
instead.
Modified sources:
1. i2c.c: Fixed the bug of i2c caused by writing START bit in SMBCTL1.
2. i2c.c: Add more debug messages for unexpected bus state.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I37dbb0e5b61f4a5ba12f0638535f8031522c1711
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322883
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. The previous EC2I module does not meet section
'7.17.5 EC2I Programming Guide'. We need to correct it to prevent
conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps
long wait states.
NOTE:
If EC is using EC2I internal bus to access PNPCFG registers while host
accessing EC ram through H2RAM interface at the same time,
the symptom will appear.
2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'.
We don't allow the host access PNPCFG registers.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and
there is no error code return.
2. To create a stress test for this change.
- EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG
registers per-10ms.
- run ectool 'version' command per-100ms.
Before the change was made, LPC will keep in long wait states
immediately.
After the change, we run the test of ectool 'version' command
over 20000 times.
Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da
Reviewed-on: https://chromium-review.googlesource.com/323563
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are hooks for chipset power sequencing but not one to indicate
that the system has reset at runtime. Add a hook for this and
implement for lm4 and mec1322. The hook is notified on any platform
reset, including those that happen on the way into S3/S5 state.
There is a new config variable added because the hook is notified in
the interrupt handler and needs a deferrable function that needs to
be added to every board.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315221
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Each pair of protect bits locks 4K, so for parts with 64K flash, don't
bother checking STM32_OPTB_WRP23.
BUG=chrome-os-partner:49354
TEST=Run flashrom to protect PD MCU (see repro steps on linked crbug),
reboot and verify system boots into dev mode with all_at_boot and
all_now protect flags set on PD MCU.
BRANCH=glados
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic375d97c30bfd68940350641c44d5535b0402a2f
Reviewed-on: https://chromium-review.googlesource.com/322823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We found the deviation of 115200 UART baud-rate is too large when core
clock is 16 or 12MHz. It causes failure during FAFT since sometime EC
could not receive correct commands to proceed test. We adjusted core
clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of
them have run FAFT and stress tests for weeks and no UART issues were
found.
Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH
and hold time directly for better i2c timing when freq is 400K. And if
freq is 100K, we introduced normal mode to handle it.
Modified sources:
1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz.
2. clock_chip.h: Set target core clock as 15 MHz.
3. uart.c: Add baud-rate support for 15/13 MHz.
4. register.h: Add new register definitions of SMBus.
5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c
timing.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322320
Reviewed-by: Shawn N <shawnn@chromium.org>
When a sysjump host command is received, there is a (usually) small
period of time when the EC has sent a reply packet back to the host, but
interrupts are still enabled. If the host sends a new host command,
STATUS_PROCESSING will be set by the EC ISR, but the host command will
never be handled due to pending sysjump. In this case, STATUS_PROCESSING
will still be set, so we need to clear it on LPC post-sysjump re-init.
BUG=chrome-os-partner:49318
TEST=Add 200ms msleep before call to interrupt_disable() in
jump_to_image(), boot to software sync, and verify host commands are
handled successfully post-sysjump and system continues to boot.
BRANCH=glados, cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759
Reviewed-on: https://chromium-review.googlesource.com/322431
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Includes support for encrypt / decrypt,
and sign / verify; padding schemes OAEP /
PKCS1; supporting bignum library.
RSA key sizes must be a multiple of 32-bits
(with the top bit set). Keying material,
input and output buffers are required to be
word-aligned.
BRANCH=none
TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316942
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L
and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs
simultaneously since EC's power rail is turned off by PMIC for a while.
VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery
mode detection.
The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset.
Use BOARD_WHEATLEY to distinguish them.
Modified drivers:
1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I96198ffb6901f0539755046ca303e94381ae7541
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320641
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support rpm mode, we use a TICK function (fan_tick_func) to
monitor tacho value and adjust PWM duty. In this version, fan driver always
enables clock source of MFT to make sure it can present real-time tacho value.
For better performance, the feedback value to adjust PWM duty is various.
We also change fan & pwm settings for SUNUN 4-pins pwm-type fan.
Modified drivers:
1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
3. fan_chip.h: Remove unnecessary default_count field of mft_t structure
4. fan.c: Add support for rpm mode
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320510
Reviewed-by: Randall Spangler <rspangler@chromium.org>
[task]
1. Copy task_wait_event_mask() function of cortex-m0.
[system]
2. Include host_command.h for host_command_pd_request_hibernate().
[i2c]
3. Update i2c handler to use task_wait_event_mask.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chromium:435611,chromium:435612
TEST=1. console commands: i2cscan, i2cxfer, and battery.
Change-Id: If5bb4407460d28c0b021ab133ca4b635ff7bc3c9
Reviewed-on: https://chromium-review.googlesource.com/320440
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We should consider the interval between the calling __hw_clock_event_set and
entering deep idle. In order to get more accurate value of deep idle time, FW
should record the time-stamp before entering deep idle and calculate the deep
idle time based on it.
Modified drivers:
1. hwtimer_chip.h: Add new function declarations for deep idle time caculation.
2. hwtimer.c: Add new functionsfor deep idle time caculation.
3. clock.c: Modified for calculating more accurate deep idle time.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Id037c4dc3564659e4ad493f2fc3ffc5d06c18b06
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320071
Reviewed-by: Randall Spangler <rspangler@chromium.org>
