The tegra 132 SOC support was removed from the coreboot codebase in
commit 9ba06995 - soc/nvidia/tegra132: remove tegra132 support
Remove the blobs since the chip is no longer used.
Change-Id: Ic4ea493b2b5bb4e337ed617c647ad330b6b254ac
Signed-off-by: Martin Roth <martinroth@chromium.org>
These are dummy files. To build working images, you'll need to fetch the
actual binaries from an existing image (or convince Qualcomm to give you
the binaries).
Change-Id: I89115b91bbe4c998c9b9854e6178e9788009b3a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Moved from a lonely directory in the coreboot source tree
Change-Id: I5312202d3068055e0297ddf5a9fa0672e9904c5a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit 832bc6f1f8.
For compliance with our binary policy (*), and to be able to run the
scripts producing the blobs without having to pull magic files from
magic places, put these "source" files back in.
(*) 2. Appropriate license (redistributable)
a. The binary must be accompanied by a distribution license. [..]
Change-Id: I99792dde209809ed8c90f5081593e38dc3b471b3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Intel's microcode is a binary that has been converted to
an array of 32bit values. Instead of converting that back
to binary on every compile, just store the microcode as
a binary in the first place, and add that binary to CBFS.
This patch adds a script that takes all current Intel microcode.h
files and produces microcode.bin files. In addition, this patch
also adds all the microcode.bin files produced by the script.
Change-Id: Ia2712b50b49685f3eb781c0c68168ea1914350f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The fake binaries *.mbn need an 8 byte header
d1 dc 4b 84 34 10 d7 73 for mbncat.py to accept them.
Add all files that will be needed for IPQ806x builds
down the line.
This will still not produce a working coreboot binary, but
it will fix compilation of coreboot.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I8cbb45eeb559f673deeefbf7692aff6b0211e59f
Please update uber-sbl.mbn from your existing coreboot image.
These are only dummy images to make the build pass.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I20be2c7c71fcad274c7ef281f430f090b282e9ee
This is done by creating a model_306ax dir. The update-microcodes
script will then automatically extract the relevant microcode.
Change-Id: Idf78088b58ad2ce9dc9e6881adf3a8ee9d2fd03c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Microcode files will need to be added to this repository before they
can be removed from the main coreboot repo. Add them in anticipation
of this change. The script was updated to pull the latest microcode.
These files were extracted using the update-microcodes.sh script, and
may not necessarily match the updates currently present in the main
repository.
Change-Id: I30d41ff31b1ebb6aaeb773c2c663d7176d27060d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Rather than simply extracting the microcode updates, also create a
microcode.h header for each model, to include the extracted microcode
updates.
This should make maintenance easier, as coreboot code will be able to
simply include the "microcode.h" files in 3dparty rather than having
to update the includes every time the microcodes are updated in here.
Change-Id: I7abd81f984b1a61aeb6041d85b366e9a45c59421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
**************************************************************************
* ATTENTION: The blobs/cpu/qualcomm/ipq8064/sbls.bin file is a
* placeholder.
* It is NOT a working IPQ8064 binary.
*
* Developers should maintain the IPQ8064 file on the flash device and be
* sure to back it up prior to overwriting it with a coreboot image.
**************************************************************************
Change-Id: Ifadede6d7851a7dfb2eada8f58752a5971f9a9aa
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Move the AGESA BLOB from the CPU directory to the PI directory to match
the organization of the Steppe Eagle directory. Convert the license
file from RTF to text so that it can be reviewed in Gerrit.
Change-Id: I2b7e499ea458939af3ed5bf4e4e8d59301733ffc
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Add AGESA BLOB, VBIOS, and xHCI BLOB into the 3rdparty repo. These
are explicitly to support AMD Embedded "Bald Eagle" processors in
an FP3 package. These BLOBs may also work with other AMD Kaveri
based processor but use with other Kaveris is not supported and has
not been tested. Use at your own risk.
Change-Id: Ia3807835fdde3b2ee76ab25cfa7943085866d794
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Add the update-microcodes.sh script in anticipation of removing the
microcode updates from the main coreboot repository.
The script is copied verbatim from main repository.
Change-Id: I4d07d48646d71d58b5be329a24352ec04ae2f02d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This is a fake binary. Run strings on it to determine the
URL of the real binary.
Change-Id: Iaebdb2336e1df3b10395031b8f19d46b7550acc6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Look into the file to find out where to get the actual bootblock
for now. This is hopefully temporary to get the coreboot build process
in place and working.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I53987a0515b00af83f959468296b4c5929ba49df
