Rename northbridge/amd/00670F00/license.txt to
northbridge/amd/00670F00/vbios_license.txt (to avoid conflict with
another file license.txt already present in soc/amd/stoneyridge),
then move northbridge/amd/00670F00/* into soc/amd/stoneyridge.
BUG=b:70785272
TEST=none, just a move.
Change-Id: I1481814e249d5daab4d6ed6c0964bf575b426bf5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The organization of 3rdparty/blobs/southbridge/amd assumes supported
features by codename. This will shortly cause problems as we deviate
from the normal released functionality.
Create new folder soc/amd/stoneyridge and move stoneyridge contents from
southbridge/amd/kern folder into this new folder. This will permit later
Stoneyridge specific changes to be separated from Carrizo.
BUG=b:69613465
TEST=None.
Change-Id: I1b76a6e6c4127ad13c608f392d619109d877914c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This update consists of two changes.
Stoney: Enable Boottime Calibration
The BTC feature is required for the SMU to correctly support
AVFS. Without it, the SMU may send unsupportable VIDs to the
regulator and cause the system to crash.
Stoney: Remove SERIRQ setup
Remove the SERIRQ setup in AGESA. It is platform specific and there
isn't an AGESA API for changing the setting. In addition to not having
an override, it was being set in amd_init_post, prior to memory setup,
so prior to any possible interrupt handler. Finally it was setting
quiet mode, which isn't supported by some LPC devices that can't
recover, once switched to continiuos mode.
A corresponding change to hudson lpc setup code in coreboot is required.
Change-Id: I66bc60957af88ce4604de0b3727ef77891beadfb
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add additional firmware blobs from the PI package to be used with
APU that are fused as "fanless" OPNs.
Change-Id: I4bc965e6c66198ee3051a77d7c6f1ef0dc9433bc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit cd1cde22ed50527c323f0b908b3541020adfa4ad)
Adjust the wording from a stale license agreement to a new and
improved version from AMD.
Change-Id: Id713a932ff0b253142315fd66f5f039f696c6ddc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add the FT4 version of the Stoney binary PI which corresponds to
the same revision level as the FP4 one. This was built from
commit c14ef54a.
Change-Id: Ifb41e03ebf64b22ef0de6a9d12943cc9df9ee1f8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 6b23fa8d79b0bcfea94bc6b723aafa36bc26e477)
Add a custom build to support Family 15h Models 70h-7Fh.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry pick from e6e15473efa0a8870306745cac334b335778bc64)
Change-Id: Icf20543a3625fde83f78adef47a5d0ef0244515a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Copy PSP blobs, keys, etc. from the PI 1.3.0.3 package. This
supports Family 15h Models 70h-7Fh.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry pick from commit e25a97d6d97afddcab356a506913d2549c8e9b34)
Change-Id: I735e155a7d08dd3630a0f4707d87a024fb094f56
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace non-ASCII characters with good values. These had consisted
of formatted single and double quotes. No content of the license
agreement is modified.
Change-Id: I73acf1b7e3ab8e12b7bf70e73b0ef09d17ff9323
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace non-ASCII characters with good values. These had consisted
of formatted single and double quotes. No content of the license
agreement is modified.
This patch does not include the file for Stoney Ridge (00670F00) as
that one contains new language from AMD. The three files here are
identical and have been copied over time.
Change-Id: I60b81bac0b5f3f8836871cc5c17e425aabc923e0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace non-ASCII characters with good values. These had consisted
of formatted single and double quotes. No content of the license
agreement is modified.
Change-Id: Iba33c2b2aa77e6dd311c2f390107c1494d678cac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Copy the generic binary image 006 and release notes from
the PI 1.3.0.3 package.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 4e6801c9a75d2b0303c68b91fe6205fb28f761a5)
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id8d8212ff4ff6a768cbf2607189e7fc391ea737b
The tegra 132 SOC support was removed from the coreboot codebase in
commit 9ba06995 - soc/nvidia/tegra132: remove tegra132 support
Remove the blobs since the chip is no longer used.
Change-Id: Ic4ea493b2b5bb4e337ed617c647ad330b6b254ac
Signed-off-by: Martin Roth <martinroth@chromium.org>
Any later AGESA binaries does not work for this board because of
commit 95b80508d9 in the blobs repo.
Change-Id: I9eaf66d6c6a3af4cb9dce7d43152afe2111720d4
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
These are dummy files. To build working images, you'll need to fetch the
actual binaries from an existing image (or convince Qualcomm to give you
the binaries).
Change-Id: I89115b91bbe4c998c9b9854e6178e9788009b3a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Moved from a lonely directory in the coreboot source tree
Change-Id: I5312202d3068055e0297ddf5a9fa0672e9904c5a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit 832bc6f1f8.
For compliance with our binary policy (*), and to be able to run the
scripts producing the blobs without having to pull magic files from
magic places, put these "source" files back in.
(*) 2. Appropriate license (redistributable)
a. The binary must be accompanied by a distribution license. [..]
Change-Id: I99792dde209809ed8c90f5081593e38dc3b471b3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Add a title for 3.
- Drop a. if there's no b.
Change-Id: I672a685e1d7a5dff7f0723da6a8a935e9f9ed469
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.1
Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the
boards can boot to Windows 10. PCIe slots, USB and NIC work.
Change-Id: Ie86bb0cf2e3cae7a9b446dfa93145ab2fce36c4f
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
While coreboot attempts to be binary free, some coreboot mainboards
require vendor binaries to support silicon and features. It is an
unfortunate fact, as silicon has become more complicated, vendors are
using more binaries to support their silicon.
This policy sets standards and expectations for vendor binaries.
Change-Id: I284b713975ac9fc4d8a19f26d20e2223f4250cbd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Update AGESA.bin and PSP to MullinsPI 1.0.0.A.
This is tested on Olive Hill Plus. The board can boot to Windows 7.
PCIe slot, USB and NIC work.
Change-Id: I67817dc59f9984019ac66ce7a9ab1a2f34e0be9e
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.0
Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the
boards can boot to Windows 8.1. PCIe slots, USB and NIC work.
Change-Id: Icb7a4f0724d9e18b22e8ffee13d19d20ddeb9dcb
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
The AMD AGESA binaryPI sources were incorrectly committed to
3rdparty/blobs. Move them from blobs to vendorcode. Commit this
after the files are committed to coreboot vendorcode/.
Change-Id: If583c15ba4f7d63df264e09573c2605824836da0
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Intel's microcode is a binary that has been converted to
an array of 32bit values. Instead of converting that back
to binary on every compile, just store the microcode as
a binary in the first place, and add that binary to CBFS.
This patch adds a script that takes all current Intel microcode.h
files and produces microcode.bin files. In addition, this patch
also adds all the microcode.bin files produced by the script.
Change-Id: Ia2712b50b49685f3eb781c0c68168ea1914350f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This file is needed for memory configuration and was forgotten in
Change I5e4b476 "northbridge/amd/pi: Add support for memory settings".
So add it now.
Change-Id: I0fb4cc8a2ba66e4d6f8cfc8ee00966ac6b94cade
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
This attribute is not supported by clang, and will cause
errors during compilation.
Change-Id: Ia4bb030e8aae8eea7c271d912a6bfec167f54410
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Add NB PState support
2. Add FchSetSpi
3. Skip CF9 warm reset in FchInitResetHwAcpiP
Change-Id: I0689bb835c29b83d947f609eaebfbe71eb54b3dd
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Fix up all the code that is using / to use >> for divisions instead.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: If53096e5b840f39b4c499254207d05aacdf32acd
Windows 7 can't boot after the graphics driver is installed.
The system hangs with a black screen screen as the OS loads.
The problem was PSP initialization in AGESA PI.
Two functions are added:
PspMboxBiosCmdDramInfo and PspMboxBiosCmdExitBootServices
This is the only change in this AGESA PI release.
Tested on Olive Hill plus with graphics driver version 14.12.
Change-Id: I7c413cd6506318d5a8fda5f1ab52a7168151affa
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
PspSecureOs_prod_CZ.sbin is useless due to
commit db08765 "AMD Kern: Fix path of PspSecureOs BLOB"
Change-Id: I58f3974979ed07beb65a20f7132607298991d508
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
1. Add const in PCIe_COMPLEX_DESCRIPTOR and EarlyOemGpioTable
The warnings are assignment discards 'const' qualifier in
src/mainboard/amd/bettong/BiosCallOuts.c and
src/mainboard/amd/bettong/PlatformGnbPcie.c
2. Change AltImageBasePtr and ImageBasePtr to VOID *
AltImageBasePtr and ImageBasePtr are two fields in AMD_CONFIG_PARAMS.
In orininal AGESA these two fiels are UINT32. This will result build
warning in agesawrapper_amdinitpost:
AmdParamStruct.StdHeader.AltImageBasePtr = NULL;
So change these two according to Steppe Eagle and Bald Eagle.
I also change the header files in binary PI code and rebuild AGESA.bin.
The new AGESA.bin is the same as befor, so I didn't upload AGESA.bin.
Change-Id: I59cf8b1bc0dc15c001f7b3ba0a5a945374663908
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Change pi/amd/00660F01/binaryPI/AGESA.c according to
commit a710941e4: amd/pi: Move AGESA cbfs access function to coreboot
Change-Id: I8c00b009a4939862a1ada912aaf850de81c133c6
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
AmdS3Save no longer exists in Carrizo.
Imc lib should move to southbridge.
Change-Id: I2c925adf4469bb53139abe48108800655db2a5fe
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
It's already defined in stdint.h and redefining it here conflicts
with coreboot proper.
Change-Id: I9a250b37b2f39278e4fdcd5c4b094457394549b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the microcde from chromium.org commit:
584219ff73ea4888995f460d2292b1b236f62c28
Change-Id: I87224206436a500e042215a844f0a8d8c042382a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Picked up from chromium.org commit:
1b2f4ca558c29b3bb5b8eb9b7d935ddf84d222ee
Change-Id: If597662cce66ff8937a6d310ecdf2bd849e258f2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Add AGESA BLOB, head files, VBIOS, xHCI, IMC and PSP firmwares
into the 3rdparty repo. These are explicitly to support AMD
Embedded "Merlin Falcon" processors in a FP4 package.
I have tested on board Bettong. Windows 7, Windows 8 and
Ubuntu 14.04 can boot.
Change-Id: I61abc61b0a837eb1e7b9bee6f6155f92d6c7419d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
The AGESA.c file in 3rdparty has cbfs access functions
for locating the AGESA binaries. coreboot access functions
need to be within coreboot where they can be updated with
cbfs changes. Move the offending function to coreboot.
Change-Id: Ic414d2c74e270548d5190e8c95e4cd7b8f3b8edd
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
