In the samus power sequence steps there is a delay of 500ms when
booting without a battery attached. This delay is currently set
to happen in the S5->S3 transition time, which seems to confuse
sequencing on some boards as we have already set DPWROK and
RSMRST and so this 500ms delay can mess up timing.
Move this delay to happen after 5V is up but before any of the
triggers to the chipset to start sequencing are set.
BUG=chrome-os-partner:31583
BRANCH=samus
TEST=boot on samus pre-DVT and DVT without a battery
Change-Id: I9519c336b121c86183c8368282f6c94b32987c16
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/241180
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On samus, set the input current limit ~200mA lower than the
value we want to accomodate hardware inaccuracy.
BUG=chrome-os-partner:34938
BRANCH=samus
TEST=load on to unit and verify using "charger" command on
ec console that the input current limit is 192mA less than
expected.
Change-Id: Ia6f82a1a622975715bd36c8c2a23e9677a6f18f0
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240751
Reviewed-by: Shawn N <shawnn@chromium.org>
Update the thermal table to account for Tj_max changing from 100C to 105C
so the thermal shutdown temperature is 104C instead of 99C.
The warn and high(prochot) values are left the same as we do want to try
and throttle with some room before the critical threshold will pull power.
This is mostly a concern in the factory where they may run without active
cooling during MLB testing.
BUG=chrome-os-partner:35483
BRANCH=samus
TEST=build and boot on samus
Change-Id: Iae55d7ca41f81e6b7250585be374fb8dd1b6533c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/241011
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Increase this timeout to 60s to allow powerd to cleanly shutdown the
system, if we boot with a low-power charger and low battery.
BUG=chrome-os-partner:35188
TEST=Manual on Samus. Deplete battery to 2% and boot system with 5V /
500mA charger attached. Verify that OS powers down before critical
battery shutdown occurs.
BRANCH=Samus
Change-Id: I9429d05efad506a855507bfb5b76de41df2aac1e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240816
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add a FIFO to log important events on the PD MCU and coming from the PD
accessories.
The retrieval of the accessories log from the accessories by the PD MCU
is not implemented yet.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:32785
TEST=execute "ectool --name=cros_pd pdlog"
before and after plugging Zinger charger.
Change-Id: If96d73e711ff6ad64cfb99bd3e4d2d8f2643f19a
Reviewed-on: https://chromium-review.googlesource.com/238854
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
This adds some temp limits from the motherboard die sensors to
use in determining the desired fan speed.
I'm also bumping the minimum PECI temp up a bit, since it varies
rapidly. At room temp the motherboard sensors will generally
request a little bit of cooling, but in cool environments it's
likely that the PECI changes will become the major annoying factor.
BUG=chrome-os-partner:34789
BRANCH=ToT,samus
TEST=manual
Watch/listen to fans. They shouldn't turn off and on as much.
Change-Id: I309132a053a052b456808e42261844dbf6442675
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240435
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Increase discharge timeout delay to 275ms, which is the new
tSrcSettle time. Also, fix fault condition so that we reset
immediately upon receiving a fault.
BUG=chrome-os-partner:35330
BRANCH=samus
TEST=load on zinger and test with firefly many 20->5V transitions
without a discharge error
Change-Id: I13bc5d77889a37390603c6922c84b264c77d79ac
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240399
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change the reads of output enable and discharge gpio's to use
the output data register (ODR) instead of reading input data
register (IDR) because we are really intending to read it's output
state, what we have set it to.
BUG=none
BRANCH=zinger
TEST=make -j buildall. load on zinger and use it normally.
Change-Id: I308bbb659aa26a9d0bca8caef6d1257fc1146ae9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240398
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If we discharge directly the output voltage from 20V to 5V under load,
an undershot happens and we dip below the 5V UVP threshold.
So when doing a down voltage transition from 20V to 5V, split it into 2
steps : a 20V->12V transition then once we are reached 12V, a 12V->5V
transition.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:33794
TEST=connect Zinger to a Firefly and an electronic load.
Using Firefly, ask for 20V->5V, 12V->5V and 20V->12V
transitions, check the VBUS waveforms on the scope.
Change-Id: Ie1e091ae6f1fee1fb7d4e3bd72edbe7491acd5ea
Reviewed-on: https://chromium-review.googlesource.com/229732
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
To ensure we respond fast enough to the Discover Identity VDM
(which timeout after 30ms), we need to pre-cache the RW hash at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35327
TEST=plug Zinger to a PD sink and check the PD protocol trace on Twinkie
Change-Id: I9decdff358dd1ab9ac373ce8bfdd0402f5e21f04
Reviewed-on: https://chromium-review.googlesource.com/240080
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Implement the new type-C connect state machine which removes
lock and hold times and adds a debounce time to make sure
CC lines settle before going into the attached state.
This also adds detection of accessories, but doesn't do anything
when an accessory is detected.
BUG=chrome-os-partner:33680
BRANCH=samus
TEST=test samus connected zinger and samus connected to samus. make
sure that the connection is always formed. also tested with a third
party with old state machine implementation and formed a connection
every time.
Change-Id: I91a7a6031bc35082cc19d7697142e4aa92ef46f2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238210
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove PWM module which is not being used in order to save flash
space.
BUG=chrome-os-partner:34489
BRANCH=samus
TEST=make -j buildall. view .map file and see we save ~760 bytes.
Change-Id: Id107fb402a60c5ac7510982f8ace6bad46fb14d0
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239912
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
History is written by the victors, except when they run out of flash
space.
BUG=chrome-os-partner:34489
TEST=Build samus_pd, check ec.RO.map and verify 756 bytes were saved.
Verify that 'history' no longer works on console and up arrow has no
function.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If512fe31f01cc35b0ef6fa60714b9df125818d64
Reviewed-on: https://chromium-review.googlesource.com/239971
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
VESA DisplayPort Alt Mode on USB Type-C Standard specifies:
When DisplayPort Configuration is not selected (and the converter is
driving its HPD output low), the converter shall track the current
state of HPD, ready for appropriate indication when DisplayPort
Configuration is subsequently selected.
Not only are we violating specification here but it also causes a race
between enabling DPout muxes to AUX line which in turn causes GPU to
timeout trying to read EDID/DPCD on occasion.
Change adds post_config function for DFPs alternate mode and in the
case of DP it sets the dp_on flag there. This allows attention
function to correctly defer HPD_HI that may accompany 'DP status' VDM
to be queued (deferred) until such time that AUX muxes are enabled
properly.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35219
TEST=manual, using hoho & dingdong
With kernel bootarg drm.debug=0x6 following cases all show these
drm debug lines:
[drm:i915_hotplug_work_func], Connector DP-2 (pin 5) received
hotplug event.
[drm:intel_dp_get_dpcd], DPCD: 12 14 c4 01 01 00 01 00 02 02 06 00
00 00 00
[drm:intel_hpd_irq_event], [CONNECTOR:38:DP-2] status updated from
disconnected to connected
case1: boot connected to external display
case2: attach dongle to external display then samus
case3: attach dongle to samus then to external display
case4: connect/disconnect rapidly on type-C side
case5: connect/disconnect rapidly on external display side.
Change-Id: I40eab797fdd5090c8ad13fae2cd053b740d9a307
Reviewed-on: https://chromium-review.googlesource.com/239420
Trybot-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Build a Twinkie firmware image with the regular Twinkie sniffer firmware
in the RO partition and a firmware behaving as a USB PD sink in the
RW partition.
The user can call the "twinkie sink" command to switch the USB PD sink
firmware in the RW partition (and call "reboot" if he changes his mind
and wants the sniffer back).
Restore the ability of building different tasklists which was broken
where the tests build was simplified.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
./board/twinkie/build_rw_variant
Try "twinkie sink" command on a Twinkie with the combined firmware.
Change-Id: Ie489ce97a774ae7a22ac639c49a3d6e412e62de8
Reviewed-on: https://chromium-review.googlesource.com/237221
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
the VCONN INA is off by default to avoid a leakage path on CC2.
Turn it on when asking for a VCONN measurement ("twinkie vconn"),
then off aftwerwards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the Twinkie command-line, "tw vconn" with the Twinkie interposed
between a Samus and a DingDong.
Change-Id: I8cd78b285512644af0824a44c735585b684fee66
Reviewed-on: https://chromium-review.googlesource.com/239212
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Power up inhibit is intended to stop the AP from booting when the
battery is in certain states. It works most of the time, but sometimes
IN_PCH_SLP_S5_DEASSERTED is already set by the time we get to S5 and we
incorrectly boot the AP.
Thinking about this more, it's better to check the battery state in G3,
before we transition to S5, to prevent the needless transition back to
G3 if power up is indeed inhibited.
BUG=chrome-os-partner:35182
TEST=Manual on Samus. Drain battery to 1% and attach charger. Press
power button multiple times and verify that AP doesn't boot. Charge
better to 2% and press power button. Verify that AP boots.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib03c3f707f9d90d0a9cb07ada3738d00e2728c32
Reviewed-on: https://chromium-review.googlesource.com/239352
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Samus should reject request for a power swap if it is not in a
dual-role mode, for instance if in S3 or lower.
BUG=chrome-os-partner:35141
BRANCH=samus
TEST=load on two samus'. turn on samus off, then request a power
swap from the samus that is on and see that it is rejected.
Change-Id: Ifb23febac967c981251c3932856e1e942818694f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238963
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
These USB type-C accessories don't have a write-protect GPIO.
Add a configure flag (CONFIG_WP_ALWAYS) to force the flash
write-protection on the dongles.
Also set the read protection (by elevating RDP to level 1),
so trying to unprotect the flash will trigger a full erase.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35088
TEST=boot Hoho,
check the flash OBR and WRPR registers:
"rw 0x4002201c" / "rw 0x40022020"
and the option bytes write-protect bits: "rw 0x1FFFF808"
dump the logical state with "flashinfo" command.
> rw 0x4002201c
read 0x40022020 = 0xffff0002
> rw 0x40022020
read 0x40022020 = 0xffff0000
> rw 0x1FFFF808
read 0x1ffff808 = 0xff00ff00
> flashinfo
Physical: 128 KB
Usable: 128 KB
Write: 2 B (ideal 2 B)
Erase: 2048 B (to 1-bits)
Protect: 4096 B
Flags: wp_gpio_asserted ro_at_boot ro_now
Protected now:
YYYYYYYY YYYYYYYY ........ ........
Change-Id: I45bbc0bce40ecc174b6b8a1ebacf4f53d2fd372d
Reviewed-on: https://chromium-review.googlesource.com/238893
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Previously there was just a memcpy_usbram that copied to
USB packet memory, and no routine to copy out. This adds
the "from" version and renames and improves to "to" version.
The improvement is that the new "to" version correctly
handles unaligned beginning and endings of the region to
be copied. These need to be read/modify/write accesses since
the USB packet ram has to be manipulated in 16-bit chunks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify that discovery-stm32f072 still enumerates and communicates
correctly over USB.
Change-Id: I94353e66ad0248d4e674abb29f9a88e979767655
Reviewed-on: https://chromium-review.googlesource.com/238764
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Change samus power supply transition delay for Raiden ports to
80ms since it may take that long to turn off the power supply
when doing a power swap.
BUG=chrome-os-partner:34525
BRANCH=samus
TEST=load onto samus, connect samus to samus and do a power swap.
Change-Id: I20c2cb78f17168a5b69780de4af5ff478f6d5f87
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238961
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For samus, on PD connection or on resume to S0, if we are a sink,
and the other side supports PR_SWAP, then attempt a power swap.
This adds callback functions into board policy file to check
and issue power or data swaps if required by the product.
BUG=chrome-os-partner:31195
BRANCH=samus
TEST=connect samus to zinger and make sure zinger always ends up
as SRC-UFP.
connect samus to samus with both in S0 and see that
they swap power roles once and not data roles.
connect one samus in S0 to one samus in S5 and see that the one
in S5 is sink. then when you boot the one in S5 it switches to a
source.
connect samus to samus with both in S0. do chgoverride 1 on one
side to start charging from the other samus. then on the same
side, turn off the machine (S5) and resume (S0), and see that it
is still charging from the other samus (ie has not switched roles
to source).
Change-Id: Ifab2465fccef77448ac4771a3c2de1c867cbbec4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238302
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Create optional config to remove 'hash' console command and undef it
for a few space-constrained boards (ryu*, samus_pd).
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34489
TEST=manual,
- compile for ryu, samus_pd and save ~400bytes
- 'hash' command no longer appears as a console command
Change-Id: I054fd4473911dd362c2c1d171ee7aaad859d893a
Reviewed-on: https://chromium-review.googlesource.com/238433
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Check the flash protection at startup, if the RDP is still at level 0
(no read protection) or if the RO partition is not write protected :
- set the write protection on the first 16KB of flash (4 LSB of WRP0)
- push the RDP to level 1, so SWD/serial monitor needs to fully erase
the part before re-writing the code or the write-protection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34935
TEST=dump the content of the option bytes.
Change-Id: I11af64365a6fbc34327b2e463eb8e2d369ffacd2
Reviewed-on: https://chromium-review.googlesource.com/238262
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Keep track of the high 32-bit of the microsecond time counter to avoid
rollback issues.
Just activate the timer "update" interrupt (aka UIE) and increment the
high word on every update interrupt.
Also disable STOP mode when we are going to roll-over during sleep to
avoid missing the event. Given that's only happening every hour, we
should not waste too much power.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34159
TEST=patch the code to set the initial TIM2 value to 0xFC000000,
wait for 67s, see the counter rolling and the high word incrementing,
then verify that Zinger is still functional.
Change-Id: I3a2f8fc09104d8ac75c581b2abcbcef99344def7
Reviewed-on: https://chromium-review.googlesource.com/238220
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
When battery is full and system is not in S0, then stop charging
and allow battery to power the system. Once battery is no longer
full and requests current, allow charging again. This is to work
around power consumption issues in our AC input path. The charge
override port is stored upon entering S3 and restored going back
to S0 so that the charge override port is not affected by this.
This also fixes lightbar so lightbar checks if battery is full
instead of checking raw percentage. The lightbar is also changed
to use the last tap direction if no charger is plugged in. And
the lightbar tap for battery threshold for turning green is
lowered to 95%.
This also moves some samus_pd board code out of interrupt handlers
and in to deferred functions to minimize time in interrupts.
BUG=chrome-os-partner:34640, chrome-os-partner:34847
BRANCH=samus
TEST=load onto samus. use battfake command from pd console to
set battery percentage. when system is in G3, see that
batt = 100% stops charging, and when batt < 100% it starts
charging again.
tested that we receive host command from EC with battery
information every time battery changes SOC.
Change-Id: Ia8e0721508e34ee3630f5e5b0c2f431a00329caf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236411
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Make large battery struct array constant to save RAM space
BUG=none
BRANCH=samus
TEST=make -j buildall. check ec.RO.map and see 96 bytes
RAM saved.
Change-Id: I181138eb79138f6e7bb25738c669232cfa0d31b7
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238211
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This will also inhibit power-on if no battery is attached.
BUG=chrome-os-partner:31127
TEST=Manual on Samus. Verify that AP continues to boot normally when
charge level exceeds CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON. Verify
that power button presses are ignored when the charge level is below
the threshold, and we return to G3. Also, verify that Samus can boot
successfully to the OS with 1% battery and a 5V @ 500mA charger attached.
BRANCH=Samus
Change-Id: I47cd3903c8cc13282fd5038f9d5fd1e310283ea7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236022
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix task_wait_event() in zinger runtime so that checking for events
fired is done with interrupts disabled to avoid getting an interrupt
that sets an event right after checking for that event.
BUG=none
BRANCH=samus
TEST=load on zinger and plug/unplug ~10 times and see successful
negotiations without any communication errors. note that without this
CL, under certain circumstances, zinger fails to respond with goodCRC
at the right time because the RX interrupt sets the event after
task_wait_event() has already checked it.
Change-Id: I2b43b8e389c6655d2a7a62b791014d1d5d678158
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238092
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add support for alternate functions for nrf51.
Add more register definitions for the nrf51.
Use assertions for conditions that should never happen.
Use BUILD_ASSERT to keep the sources in sync.
Add three more GPIOs to hadoken.
BQ27621_GPOUT - Configurable output from the fuel gauge.
LID_PRESENT_L - The input for the hall sensor.
IND_CHRG_DISABLE - The output to control inductive charging.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used gpioget and magnets for LID_PRESENT_L
Used fuel gauge console commands to trigger BQ27621_GPOUT
Tested the assertions with gdb
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I508f79ae45127104fa14f9f75fbf545f226387e4
Reviewed-on: https://chromium-review.googlesource.com/234286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
With the type-c connector, it's common for VBUS to make contact before
D+/D-, which can lead to charger misdetection. To work around this, add
a 200ms delay and trigger re-detection when a charger is inserted. This
should fix most misdetects due to unintentional slow plug (though it's
still possible to misdetect if insertion is deliberately very slow).
BUG=chrome-os-partner:34584
TEST=Manual on Samus. Plug in Apple charger 20 times, verify that it is
always detected correctly. Deliberately plug in slowly, verify it is
detected as 500mA SDP port. Repeat tests with various other CDP / SDP
ports to verify detection never over-currents and always indicates a
charger is plugged (or not plugged) correctly.
BRANCH=Samus
Change-Id: I8a776f516d8e7f0cedcb9d8579239eba641cab09
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237241
Reviewed-by: Alec Berg <alecaberg@chromium.org>
For factory testing, we need a way to simulate unplugging type-C cable.
To do so, we disable VBUS output and pull-up/pull-down on CC lines on
Plankton, so that the CC lines become floating.
BRANCH=None
BUG=chrome-os-partner:32163
TEST=Connect Plankton to Ryu. Try 'fake_disconnect' as SRC/SNK.
Change-Id: I73a7355e078b6aed4b7d281d480e0aedbc8c2db0
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229662
Reviewed-by: Pin-chih Lin <johnylin@chromium.org>
Tested-by: Pin-chih Lin <johnylin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
