Current fast charge assumes only one battery voltage threshold range for
charger profile override. However we have multiple battery voltage
threshold ranges for few batteries hence added a code which can consider
multiple battery threshold ranges and choose respective charge profile.
BUG=chrome-os-partner:62653
BRANCH=none
TEST=Manually tested on Electro. Manipulate smp_cos4870 & sonycorp
battery voltage & temperature ranges and observed correct charge
profile is selected.
Change-Id: Icddc047e608cc8f63cd0c19be716e0f7908ca715
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/438804
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a host command to get PD chip info.
For PS8751, tcpci_get_chip_info will fail if the chip is in
low power mode. It can be woken up by reading a random register
first then wait for 10ms.
This code doesn't have the wake-up read to avoid 10ms delay.
Instead, we call this function immediately after the chip is
initialized because it'll gurantee the chip is awake.
Once it's called, the chip info will be stored in cache, which
can be accessed by tcpc_get_chip_info without worrying about
chip states.
localhost ~ # ectool pdchipinfo 0
vendor_id: 0xaaaa
product_id: 0x3429
device_id: 0xad
fw_version: 0x15
localhost ~ # ectool pdchipinfo 1
vendor_id: 0x1da0
product_id: 0x8751
device_id: 0x1
fw_version: 0x37
BUG=chrome-os-partner:62383
BRANCH=none
TEST=ectool pdchipinfo 0/1. make buildall
Change-Id: I3f1667d00ce1826936d90882ada1df6ed6b0ea37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433166
Add driver for acc sensor ST lis2dh/lis2dh12
Support interrupt management for FIFO watermark
Starting to share common code with other devices
like lsm6dsm/lsm6dsl (acc/gyro) or new lis2mdl (mag)
TODO: Add all embedded functions support (click,
tap and so on)
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc seems ok: can successfully change ODR and
full scale range. Also FIFO and interrupt tested
Device tested is lis2dh (lis2dh12 simply differs for low
pin count but share the same registers)
Change-Id: I16abeac3f139a604094b38d8d8b857a62c93a242
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/412700
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
If CONFIG_SPI_NOR_SMART_ERASE is defined will read the sector/block
to be erased first and only initiate the erase operation if not
already in an erased state. The read operation (performed in
CONFIG_SPI_NOR_MAX_READ_SIZE chunks) is aborted early if a
non "0xff" byte is encountered.
Reduced erase time of a mostly erased EEPROM from 44s to 20s (16MB
Winbond part) / 1m22s to 40s (32MB Macronix part) @24MHz.
BUG=None
BRANCH=None
TEST=Built all targets. Successfully flashed various EEPROM images.
Change-Id: I369b1fcf72140663b8dbce5a469ebad27f7571ec
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/437988
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
If both nvmem partitions are corrupted, then nvmem_reinitialize() will be
called and commits must be enabled prior to this so that
nvmem_release_cache() succeeds.
BRANCH=none
BUG=chrome-os-partner:62531
TEST=On Reef after a successful boot, corrupt nvmem partitions using
the following console commands:
flasherase 0x7d000 0x3000
flasherase 0x3d000 0x3000
Then reboot via H1 console and verified via the console that the nvmem
partitions were reconfigured.
nvmem_find_partition:302 partiton 0 verification FAILED
nvmem_find_partition:302 partiton 1 verification FAILED
[0.025928 nvmem_find_partition: No Valid Partition found, will
reinitialize!]
[0.127752 Active Nvmem partition set to 1]
Then verfied that TPM was functional and the system booted booted into
the kernel. Without this CL this set of actions would always result in
going in to recovery mode due to TPM failure.
Change-Id: If1691b179e19cb37f0fc6ba893219dd8c02f2cf5
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439368
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The cr50 needs to be aware of the power state of the system and of the
moment when the AP is reset, because this is when the TPM needs to be
reset too.
Arm and x86 platforms provide different hints in these cases.
In case of x86 there is a single signal cr50 can rely on: PLT_RST_L.
This active low signal is asserted when the system is going into any
power state deeper than s0ix. The cr50 can fall into deep sleep when
PLT_RST_L is asserted, and has to wake up and reset the TPM when this
signal is deasserted. There could be other wake triggers, but the tpm
should not be reset unless PLT_RST_L is inactive. It is also important
not to fall into deep sleep when PLT_RST_L is pulsed to reboot the
system.
In case of ARM there are two separate signals. Deasserting SYS_RST_L
signal is the trigger to reset the TPM, The GPIO_DETECT_AP going low
for a duration of time is the indication of the AP going into some
kind of sleep mode. The ARM case requires more clarification.
This adds run time configuration of the the sleep state control input.
Once the input turns low, the CHIPSET_SHUTDOWN signal is sent and deep
sleep mode is enabled. Again, this will require adjustment for ARM
platforms.
The wake from deep sleep state is controlled by the wake pins as
before, but by level instead of edge. This makes sure that in case the
trigger for deep sleep goes away while deep sleep preparation is under
way, the device resumes immediately instead of getting stuck missing
the edge.
The TPM_RST_ input is now triggering interrupts on deassertion
- this is the moment when the TPM needs to be reset. The ISR is being
renamed accordingly.
The processing previously happening inside the ISR is being moved into
a deferred function running on the hooks task context.
There is no need to invoke TPM reset related functions from the PMU
wake up ISR anymore.
BRANCH=none
BUG=chrome-os-partner:59007
TEST=as follows:
1. make buildall -j succeeds
2. started on Reef, still in progress after 100 iterations, early to
call
suspend_stress_test --suspend_min 40 --suspend_max 45 \
--wake_max 15 wake_min 10
(note that reef does not fall into s3 any more, so the test does not
verify H1 deep sleep)
3. modified the target to fall into s3 during the test and
successfully repeated it for 100 iterations
4. tried battery disconnect a few times and observe successful boot.
Change-Id: Ica06ec0d363b53eede3be327404ff5807fa3a610
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/436865
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
All boards have been transitioned to charge_state_v2.c
So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and
CONFIG_CHARGER_TIMEOUT_HOURS can be removed
BUG=chrome-os-partner:36272
TEST=make -j buildall
BRANCH=none
Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a
Reviewed-on: https://chromium-review.googlesource.com/435467
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The INAs are only used for development and testing
purposes. Therefore, the 3.3V rail to the INAs is off by default and
the I2Cm module is not enabled. Enabling INA power and connecting the
I2Cm module was done at the beginning of each USB to I2C request. The
problem with this approach is that INA measurments didn't always
succeed due to not enough time for the INAs to initialize.
Rather than add some arbitrary delay, it is better to tie the INAs to
when rdd is attached/detached. It is only when rdd is attached that
the INAs will be accessed, so there is no need to enable/disable for
each individual I2C transaction.
This CL ties the enabling/disabling of the INA and I2Cm module to the
rdd state. This change makes the previous use of
usb_i2c_board_enable() and usb_i2c_board_disable() obslete.
BRANCH=none
BUG=chrome-os-partner:62375
TEST=manual
Connect servo with suzyq connected:
sudo servod -p 0x5014 -b eve -c eve_r0_inas.xml
Then execute single INA reads dut-control pp3300_dx_edp_mv and verify
that it returns meaningful numbers. Without this CL single reads via
dut-control would always return 0.
Change-Id: I799552bfd0701efd1828a0d720ac2a6cedee5ca1
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/436864
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The nvmem_release_cache() function checks if there is a pending write
and refuses to release the lock if so. It should also be checking if
submits have need suspended, as the task suspending commits is holding
the lock and is supposed to release it explicitly when done.
BRANCH=none
BUG=chrome-os-partner:62531
TEST=verified that the message reporting attempts to commit when cache
is unlocked is not showing up at startup any more,
Change-Id: I5a63e7421cdd4a6b11dddff3103e1d63e0be0e65
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/437758
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The timerinfo command shows the number of microseconds since boot,
expressed as a hexadecimal value. Some of us are not as good in
converting hexadecimal seconds value into decimal number of seconds
and microseconds. This patch adds the decimal value to the output.
BRANCH=none
BUG=none
TEST=verified that timerinfo output makes sense:
> time
Time: 0x000000000b66d280 us, 191.287936 s
...
> time
Time: 0x000000000caec680 us, 212.780672 s
Change-Id: I3bd4ba16f3cfb74ba8fcec4899fbff0ab259007c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/436804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
During shutdown sequence sensor rails can be powered down asynchronously
to the EC hence EC cannot interlock the sensor states with the power down
states. To avoid this issue, defer switching the sensors rate with a
configurable delay if in S3. By the time deferred function is serviced,
if the chipset is in S5 we can back out from switching the sensor rate.
BUG=chrome-os-partner:61489
BRANCH=none
TEST=Manually tested on Electro. Put the device in S5 and observed
no I2C errors printed on EC the console.
Change-Id: I40b75ebbf0d05fafffdfd535962423c3960fafbf
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/433338
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
charge_ramp needs to make a decision based upon the VBUS level on one
specific port - the port that is ramping. The VBUS level on any other
charge ports (if present) is not relevant.
BUG=chrome-os-partner:54099
BRANCH=reef, gru
TEST=With subsequent patches, verify charge_ramp success with a variety
of BC1.2 chargers.
Change-Id: Ie0a51a577e2b7491222560cd08dd5321ff3b7975
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435561
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
During TPM I2CS stress testing as described in chrome-os-partner:59191
there were instances of write mismatch errors. Previously, there was a
CPRINTF for this condition. The CPRINTF being in the i2cs ISR then
affects any subsequent i2cs activity and can create a cascade of
errors.
To avoid this issue, added a counter to track these instances and made
it to be retrieved similar to the fifo adjust counter.
BRANCH=none
BUG=chrome-os-partner:57338,chrome-os-partner:59191
TEST=manual
Ran the stress test as described in chrome-os-partner:59191 and found
that when the write mismatch occurred the counter ticked up by 2 where
before there would be numerous console log prints of the same error.
Change-Id: I2837d02037e2f47b5bd4b001d3394ad6eb4bd92c
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410032
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic8db5c706d82f7ca2ded2e90129747e7fbefdb38
Reviewed-on: https://chromium-review.googlesource.com/427959
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I49ea5fc27a7f11f66daba485a87d0dfe7d0c770f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427408
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
tpm_reset just requests a tpm reset it doesn't reset the tpm. Rename the
function to reflect that.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I6f4763b5de578a8cf263b2fac98fad3af2c25d65
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434245
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
With introduction of encryption it is becoming impossible to read
NVMEM contents directly from flash. Decrypting the contents each time
there is a read request creates a significant performance hit. NVMEM
needs to be rearchitecture such that there is no need to run
decryption each time NVMEM read is performed.
This patch does just that, implementation details are described in the
header comment in common/nvmem.c.
To reduce memory impact the size of NVMEM is being decreased from 16K
to 12K. This is acceptable because eviction objects stored in NVMEM
serialized now, which dramatically reduces NVMEM size requirements.
The TPM2 NVMEM size definition must be kept in sync.
Another optimization this change introduces is bypassing writing into
the flash if NVMEM contents did not change, which is verified by
examining the hash of the cached storage.
A test is added to verify that the new commit scheme works as
expected, and the nvmem test is re-introduced to the list of test ran
on each 'make buildall'.
CQ-DEPEND=CL:433839
BRANCH=none
BUG=chrome-os-partner:62260,chrome-os-partner:62421
BUG=chrome-os-partner:62437
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I177daa3ceb4fd7aac299ca26b4506b863e31b946
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On ANX port connecting hoho and issuing hard reset
never recovered. From TCPCI spec R1.0.4.7.2 "TCPM
writes to the RECEIVE_DETECT register to enable PD
message passing". This was missing when the port sent
HARD RESET when it acts as SRC.
BRANCH=none
BUG=chrome-os-partner:61377
TEST= On Electro, on anx port, connect hoho and issuing
pd 0 hard successfully recovers from hard rst
Change-Id: Ia2cfcaf52b88fbc24ee702c6a089389400eb42d1
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/433387
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
- Modified src attach state to enable vbus when debug accessory is
detected.
- servo_v4 has two pd ports, but each port requires a different default
power role. Port 0 can only ever be a SNK, but port 1 which acts is
intended to be a DTS port should default to a SRC so it can be be a
source debug accessory. It may also act as a sink debug accessory, but
is not intended to toggle automatically but will swap roles if
necessary via pd role swap messaging.
- Add hook for ccd enable/disable for DTS mode
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual Verfied that can still build servo_v4 project. All changes
in this CL are contingent on config option CONFIG_USB_PD_DTS being enabled.
Change-Id: Iab968b6fbdfc8f2d155c4f8618921b32f313b9ec
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428308
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In Sink mode, on the receipt of a GotoMin message,
reduce the current consumption to some minimum level.
BUG=chrome-os-partner:33688
TEST=Manual testing
Used a Kevin, with test routine, to test GotoMin feature
on another Kevin unit.
Test routine:
if (!strcasecmp(argv[2], "gm")) {
ccprintf("send goto min\n");
send_control(port, PD_CTRL_GOTO_MIN);
send_control(port, PD_CTRL_PS_RDY);
}
Kevin with GotoMin feature:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4277mV / 3000mA, max 5000mV / 3000mA / 15000mW
Port 1: Disconnected
After Test routine is executed:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4906mV / 500mA, max 5000mV / 500mA / 2500mW
Port 1: Disconnected
BRANCH=none
Change-Id: Iaac6e19706ceb10ccaff4d602d63fc086c808c8f
Reviewed-on: https://chromium-review.googlesource.com/425728
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Servo_v4 requires the ability to have a different default state per
port. In previous devices, the assumption was that each supported port
had the same default usb pd state and power role. This CL moves the
by the default power role which in turn is derived from
CONFIG_USB_PD_DUAL_ROLE. In addiiton to moving the location, it now
uses 'port' as argument so it can be port specific if required.
PD_DEFAULT_STATE was a board.h specific config, but in practice each
instance used to date was set to PD_STATE_SNK_DISCONNECTED if
CONFIG_USB_PD_DUAL_ROLE was defined and set to
PD_STATE_SRC_DISCONNECTED otherwise.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual run 'make -j buildall' to verify that all instances of
PD_DEFAULT_STATE were removed.
Change-Id: Iaf40718668732f525485ed7942ee7fc246d3f75d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431787
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch makes incompatible changes to the nvmem layout: the header
is increased to accommodate a 16 byte sha ans a 16 byte padding for
future extensions.
The layout version field is also introduced to make it easier to track
changes in the future. When calculating SHA the entire partition above
the SHA field is processed. Encryption covers everything above the
header.
Introducing encryption makes it impossible to use flash contents
directly for read and compare operations.
The nvmem_setup function is modified to use the nvnem_save() instead
of writing into the flash directly.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I50b148ac0dc6bc924f4d65c67bc6610100d9dfc0
Reviewed-on: https://chromium-review.googlesource.com/428691
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On boards based on the g chip cryptographic functions come from
hardware, they should be implemented in chip/g as opposed to a
particular board.
The common modules (like nvmem) should be using some generic API,
which hopefully will be implemented by other chips, or could be
replaced by a purely software implementation where crypto hardware
support is not available.
Crypto API definition is being added in include/ and the g chip
implementation (a wrapper around dcrypto functions) is being added in
chip/g.
test/nvmem_vars.h needed to be edited to avoid conflict with
<string.h>.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=make buildall -j still passes. Booting reef with the new image
works fine too.
Change-Id: Ifef281215f89239966882ecbe3e90c8351b9b91a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431313
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
With upcoming versioning of NVMEM contents let's replace term
'version' with term 'generation' in the existing nvmem implementation.
Generation would allow to tell between two instances of NVMEM stored
in flash memory. The upcoming version field in the header will be used
to tell between different nvmem layouts.
This patch was created by invoking the following command:
sed -i 's/VERSION/GENERATION/g;s/version/generation/g' \
common/nvmem.c include/nvmem.h test/nvmem.c
and then editing a few remaining capitalized instances.
This also fixes nvmem test broken by an earlier patch.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=the following tests succeed:
make buildall -j
TEST_LIST_HOST=nvmem make runtests
booitng reef with cr50
Change-Id: I96e52dc93ca7c52c55794ba3e8c2774571212de0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431312
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Each device keeps track of the last known state. If device_set_state
updates the device state to a new known state, then return true. Cr50
uses this returned value to check if the state has changed instead of
calculating it itself.
BUG=none
BRANCH=none
TEST=device detection still works
Change-Id: I8afac178c2c731def6f4f62ff7023fe169ec1479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously in motion lid, we only considered the lid angle as unreliable
when the hinge is too closely aligned with the direction of gravity.
However, there are other cases where the lid angle can be unreliable.
For example, when the device is being shaken and is under acceleration
that's not solely due to gravity.
This commit adds some more checks for a reliable lid angle measurement.
- Checking if the device is significant motion by checking the
deviation of the magnitudes of the base and lid vectors.
- Making sure that the calculated angles agree with the current state
of the lid switch.
BUG=chrome-os-partner:59480
BUG=chrome-os-partner:59203
BRANCH=gru,cyan,glados,oak
TEST=Flash kevin; use ectool motionsense lid_angle and monitor the
instantaneous lid angle. Verify that unreliable is reported for cases
where the device is under significant motion.
TEST=Flash kevin; use evtest to monitor the tablet mode switch. Verify
that tablet mode switch is much more robust.
Change-Id: I4bd9e818e617b056364cce2e46385e743a7522d4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430344
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
From the USBC spec 1.2 "Table 4-14 Precedence of power source usage"
USB Type-C 3.0 A & 1.5 A takes precedence over BC1.2 hence updated
the power supplier priority of charger manager.
BUG=chrome-os-partner:61420
BRANCH=none
TEST=Manually tested on reef. Donette bottom port can switch
from 1.5A to 3A upon high load.
Change-Id: Iff936d6a8643e88e0b2738251254e896fe8562fe
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/430153
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
This patch mostly is rearranging the code to make it easier to add
encryption layer in the upcoming change.
One substantial change is making sure that in case when NVMEM contents
are corrupted for whatever reason, the initialization function
re-creates a blank NVMEM space; it was just bailing out before not
leaving any initialized partitions behind.
There is no need in two separate tables - one for base absolute
addresses of the NVMEM partitions, and one for their flash memory
offsets, one can be easily derived from the other.
Code erasing the destination partition, calculating the SHA1 of the
new blob and writing it into the flash was separated into own
function.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=make buildall -j still passes (which means NVMEM tests succeed).
TPM TCG test suite also passes.
Change-Id: I378265d8b49b81398aece2eadf9698abb05caaa1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428172
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Updating variable name from smi_enabled to
power_button_pulse_enabled, which is a more accurate
description of the intended functionality.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot reef and try using power button for selection
during the detachable menus and ensure that the
DUT doesn't turn off.
Change-Id: Ia04e032818c73439d2aeacdb8fcabbe3bce7c151
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/429070
Reviewed-by: Duncan Laurie <dlaurie@google.com>
VDO_CMD_GET_LOG is sent for each port from a host command handler, so we
must ensure that it returns quickly to prevent host timeout.
BUG=chrome-os-partner:61910
BRANCH=gru
TEST=Manual on kevin, attach hoho and verify 'cros-ec-spi' timeout
errors are not seen every 60s. Also verify that zinger pdlogs are
correctly retrieved.
Change-Id: Ie0466a8b614ec6bfe5874cde9d700e80a15d298e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428164
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Relying on the AP sending a PCR read as an indication of the completed
boot process does not work on the resume path. Let's just enable
commits 3 s after they were stopped to process tpm reset.
BRANCH=none
BUG=chrome-os-partner:61795
TEST=observed the following on the cr50 console on a reef during reboot:
[0.018692 tpm_init]
tpm_manufactured: manufactured
[0.021180 tpm_reset_now: done]
.
.
[1.166496 Skipping commit]
[1.425888 Skipping commit]
[1.439112 Skipping commit]
.
.
[3.021892 Committing NVMEM changes.]
and verified that reef booted normally.
Change-Id: I5f64fe24b961a9d0366f8e4f40a0e44d4e7263fa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427328
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Specifically, we are using a bit to disable the
SMI pulse on x86 systems so that we can use the
power button for menu selection.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=Try running with depthcharge sending the host command
during detachable FW menus and making sure power
button select doesn't turn off device on reef.
Change-Id: I4a68cf514d514a4abe98beb99e7934d6fb0f44bd
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
A valid charge port is always detected as VBUS supplier type, 'USB charger'
can detect the same port as BC1.2 DCP supplier type & also 'TCPC' can
detect the same port as TYPEC supplier type. Thus a valid port is detected
as 2 or 3 supplier types. Depending on the supplier's priority and the
power that the supplier can provide, charge manager choses the charge
supplier type of the port.
If the USB charger detected supplier is BC1.2 DCP and the TCPC detected
supplier is TYPEC then the supplier can provide stable current from TYPEC
supplier's advertised current hence start ramping from TYPEC supplier's
advertised current.
BUG=chrome-os-partner:61420
BRANCH=none
TEST=Manually tested on reef. Donette bottom port can switch
from 1.5A to 3A upon high load.
Change-Id: I871eca3ae4041f00bb3fd50e6aa939643f30a1f2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427961
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When depthcharge invokes a Host command that needs EC to access
flash, the response is delayed by approx 150 ms because EC is
busy with another flash operation to determine size of RW image
for computing hash. We can eliminate this delay and also speed up the
flash operation by using the same mechanism that is used for mec1322
based designs which also use external SPI flash.
The changes are:
a) We access 4 bytes from SPI flash at a time instead of a single byte
b) We split flash accesses into smaller parts which means that mutex lock
is acquired for a short duration.
BUG=chrome-os-partner:59875
BRANCH=none
TEST=make buildall -j
After sysjump to RW, in EC Log the "hash start" is printed approx
120 ms earlier.
Change-Id: Icb633379c992e795ba40eaf54fe9ec31747d4be6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/426016
Reviewed-by: Shawn N <shawnn@chromium.org>
To avoid SRAM footprint, let's use dynamic memory allocation in
nvram_vars. No one is using this module yet, but the cr50 use case is
coming up.
BRANCH=none
BUG=chrome-os-partner:61107
TEST=make buildall -j passes
Change-Id: I21534430217ad387a3787fcc127da596a1b48e03
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426088
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit adds a "spoof" mode feature to the motionsense stack. It
allows the user to arbitrarily set the outputs of the sensor in order to
"spoof" the readings of the sensor. This can be useful in emulating
tablet mode or device rotations. A command is available from the EC
console named `accelspoof` and there is a corresponding motionsense
command in ectool called `spoof`.
The usage is as follows:
- EC console
> accelspoof [id] [on/off] [X Y Z]
- ectool
# ectool motionsense spoof -- [id] [0/1] [X Y Z]
If on or off(or 0/1) is not specified, the current spoof mode status of
the sensor is returned. If on is specified, but no components are
provided, the sensor will lock the current values and provide those as
the spoofed values. If the components are provided, those will be used
as the spoofed values.
BUG=chromium:675263
BRANCH=cyan,glados,gru,oak
TEST=Flash a DUT with accels. From AP console, run `ectool motionsense
lid_angle` in a loop, use 'accelspoof' EC console command to set spoofed
values. Verify that the angle is fixed regardless of the actual angle
of the DUT.
TEST=Flash a DUT with accels. From AP console, use `ectool motionsense
spoof` to spoof values and verify that `ectool motionsense` reflects the
spoofed values. Test with both provided component values and no
component values.
Change-Id: Ie30688d22f38054e7243b1af493a3092b2cdfb72
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/421280
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
AverageTimeToFull() and AverageTimeToEmpty() are the predicted time based
on the AverageCurrent(), these do not reflect the instant time of charging
or discharging. Hence we observe huge number of time (1092h because
register has 65535) to full time when battery starts accepting current
upon reaching 100%. To overcome this issue, explicitly checking if the
AverageTimeToFull() and AverageTimeToEmpty() register values are updated
with the valid data.
BUG=chrome-os-partner:60802
BRANCH=none
TEST=Manually tested on Reef. Charge the battery to 100%, once the
battery starts accepting current again observed time to full
is not huge number.
Change-Id: I6d6c21b72ab824dbe47e44e1e77f1c5319ac2720
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/425324
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chromium:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
BOARD with host commands and private host commands
0004d0ec R __hcmds
0004d0ec R __host_cmd_0x00000x0000
0004d0f8 R __host_cmd_0x00000x0001
0004d104 R __host_cmd_0x00000x0002
0004d110 R __host_cmd_0x00000x0003
0004d11c R __host_cmd_0x00000x0004
0004d128 R __host_cmd_0x00000x0005
0004d134 R __host_cmd_0x00000x0007
0004d140 R __host_cmd_0x00000x0008
0004d14c R __host_cmd_0x00000x000a
0004d158 R __host_cmd_0x00000x000d
0004d164 R __host_cmd_0x00000x0010
0004d170 R __host_cmd_0x00000x0011
0004d17c R __host_cmd_0x00000x0012
0004d188 R __host_cmd_0x00000x0013
0004d194 R __host_cmd_0x00000x0015
0004d1a0 R __host_cmd_0x00000x0016
0004d1ac R __host_cmd_0x00000x0017
0004d1b8 R __host_cmd_0x00000x0087
0004d1c4 R __host_cmd_0x00000x008c
0004d1d0 R __host_cmd_0x00000x008f
0004d1dc R __host_cmd_0x00000x0092
0004d1e8 R __host_cmd_0x00000x0093
0004d1f4 R __host_cmd_0x00000x0097
0004d200 R __host_cmd_0x00000x0098
0004d20c R __host_cmd_0x00000x00b6
0004d218 R __host_cmd_0x00000x00d2
0004d224 R __host_cmd_0x00000x00d3
0004d230 R __host_cmd_0x3E000x0000
0004d23c R __host_cmd_0x3E000x0002
0004d248 R __evt_src_EC_MKBP_EVENT_HOST_EVENT
0004d248 R __hcmds_end
BOARD with host commands only
100bc888 R __hcmds
100bc888 R __host_cmd_0x00000x0000
100bc894 R __host_cmd_0x00000x0001
100bc8a0 R __host_cmd_0x00000x0002
100bc8ac R __host_cmd_0x00000x0003
100bc8b8 R __host_cmd_0x00000x0004
100bc8c4 R __host_cmd_0x00000x0005
100bc8d0 R __host_cmd_0x00000x0006
100bc8dc R __host_cmd_0x00000x0007
100bc8e8 R __host_cmd_0x00000x0008
100bc8f4 R __host_cmd_0x00000x0009
100bc900 R __host_cmd_0x00000x000a
100bc90c R __host_cmd_0x00000x000b
100bc918 R __host_cmd_0x00000x000d
100bc924 R __host_cmd_0x00000x0010
100bc930 R __host_cmd_0x00000x0011
100bc93c R __host_cmd_0x00000x0012
100bc948 R __host_cmd_0x00000x0013
100bc954 R __host_cmd_0x00000x0015
100bc960 R __host_cmd_0x00000x0016
100bc96c R __host_cmd_0x00000x0017
100bc978 R __host_cmd_0x00000x0025
100bc984 R __host_cmd_0x00000x0026
100bc990 R __host_cmd_0x00000x0029
100bc99c R __host_cmd_0x00000x002a
100bc9a8 R __host_cmd_0x00000x002b
100bc9b4 R __host_cmd_0x00000x002c
100bc9c0 R __host_cmd_0x00000x0044
100bc9cc R __host_cmd_0x00000x0045
100bc9d8 R __host_cmd_0x00000x0046
100bc9e4 R __host_cmd_0x00000x0047
100bc9f0 R __host_cmd_0x00000x0061
100bc9fc R __host_cmd_0x00000x0062
100bca08 R __host_cmd_0x00000x0064
100bca14 R __host_cmd_0x00000x0065
100bca20 R __host_cmd_0x00000x0067
100bca2c R __host_cmd_0x00000x0087
100bca38 R __host_cmd_0x00000x008c
100bca44 R __host_cmd_0x00000x008d
100bca50 R __host_cmd_0x00000x008f
100bca5c R __host_cmd_0x00000x0092
100bca68 R __host_cmd_0x00000x0093
100bca74 R __host_cmd_0x00000x0096
100bca80 R __host_cmd_0x00000x0097
100bca8c R __host_cmd_0x00000x0098
100bca98 R __host_cmd_0x00000x0099
100bcaa4 R __host_cmd_0x00000x009e
100bcab0 R __host_cmd_0x00000x00a0
100bcabc R __host_cmd_0x00000x00a1
100bcac8 R __host_cmd_0x00000x00a8
100bcad4 R __host_cmd_0x00000x00a9
100bcae0 R __host_cmd_0x00000x00b6
100bcaec R __host_cmd_0x00000x00b7
100bcaf8 R __host_cmd_0x00000x00d2
100bcb04 R __host_cmd_0x00000x00d3
100bcb10 R __host_cmd_0x00000x00db
100bcb1c R __host_cmd_0x00000x0101
100bcb28 R __host_cmd_0x00000x0102
100bcb34 R __host_cmd_0x00000x0103
100bcb40 R __host_cmd_0x00000x0104
100bcb4c R __host_cmd_0x00000x0110
100bcb58 R __host_cmd_0x00000x0111
100bcb64 R __host_cmd_0x00000x0112
100bcb70 R __host_cmd_0x00000x0113
100bcb7c R __host_cmd_0x00000x0114
100bcb88 R __host_cmd_0x00000x0115
100bcb94 R __host_cmd_0x00000x0116
100bcba0 R __host_cmd_0x00000x0117
100bcbac R __host_cmd_0x00000x0118
100bcbb8 R __host_cmd_0x00000x011a
100bcbc4 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcbc4 R __hcmds_end
BRANCH=none
Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb
Reviewed-on: https://chromium-review.googlesource.com/419702
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch eliminates NVMEM commits at system startup, namely between
the moment the TPM is reset and the moment the AP is trying to read a
PCR (which is an indication of the AP having booted into OS).
To avoid losing NVMEM changes in case TPM is reset before PCR Read
command is issued, pending changes (if any) are saved before TPM reset
is processed.
For the same reason TPM reset invocation is being added to the hard
reboot path; this will kick in when there is a restart after cr50
firmware update.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=with instrumented coreboot/depthcharge observed the following
execution times for various TPM command issued at startup
command 0x144, 15203 us
command 0x14e, 11814 us
command 0x182, 12461 us
command 0x182, 12456 us
command 0x138, 11503 us
command 0x138, 11512 us
command 0x14e, 14648 us
command 0x14e, 12597 us
command 0x121, 11353 us
which totals 113 ms and shaves more than 200 ms off the boot time.
Change-Id: Ic52309291fdb9c3ede96e0ad015ad9fc076bddc5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424063
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
The new code allows to replace the existing one buffer at a time
shared memory facility with a malloc/free implementation. A new
configuration option is being provided (CONFIG_MALLOC).
The names of functions allocating and freeing memory are not being
changed to allow to switch between the two implementations seamlessly.
A double linked list of buffers is used to keep track of free and
allocated memory. During initialization the entire free memory block
is considered a single free buffer. No allocations/frees are allowed
from within interrupts. The control structures are protected by a
semaphore, so allocate and free invocation could be blocking.
A test is added which randomly allocates and frees memory, continuing
until all branches in the allocate and free functions are taken.
BUG=chrome-os-partner:
TEST=make buildall -j succeeds, which includes testing the new
malloc/free implementation.
Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We need 2 accelerometer for tablet mode. If one of them is not working,
disable tablet mode. We will stay in clamshell mode, lid angle will be
always unreliable.
BUG=chrome-os-partner:61141
TEST=On kevin with a single sensor. Check we are in clamshell mode
when rebooting the EC.
BRANCH=kevin
Change-Id: I7bf6cdc9d85370fce20e5183622b4bc18f4f5f99
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix issue where the block is calculated wrong since the offset that gets
added is wrongly EEPROM_BLOCK_COUNT_PSTORE which is the number of
total blocks rather than the starting block given by
EEPROM_BLOCK_START_PSTORE.
TEST=Build test, ran on board with stubbed out functions.
BUG=none
BRANCH=none
Change-Id: Ide4839845353c2b9f95a37eb689c8d800169bb22
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/424182
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added common code for charger profile override for fast charging.
Fast charging configs can be defined in the respective board battery
file and use the common code for imposing the custom data.
BUG=chrome-os-partner:59393
BRANCH=none
TEST=Enabled the config on Reef. Manually overrode the temperature
and voltage. Observed correct charge profile config is selected
for each tests.
Change-Id: I075d271258470b98d38e4d5395d749469d3fd469
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407928
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
