We're using fusb302 rev. >= B now, so let's remove rev. A support.
BUG=chrome-os-partner:57492
BRANCH=none
TEST=Manuel
- plug USBC->DP cable into TV then into kevin
localhost ~ # ectool usbpdmuxinfo
Port 0: DP INV
- plug USBC->DP cable into kevin then into TV
localhost ~ # ectool usbpdmuxinfo
Port 0: DP INV
- unplug USBC->DP cable from TV
Port 0: OPEN INV
- plug USBC->ETHERNET into kevin and verified that network
displayed ethernet
Change-Id: Ia84dc2480c1a8b003ab8dfdcdaa9f82f6d429e4b
Reviewed-on: https://chromium-review.googlesource.com/388925
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1.ANX3429 have CC Rx buffer, when the partner sent one message,ANX3429
received this message into Rx buffer and triggered an interrupt to
inform (TCPM), at this moment Reef sends a CC message before reading
CC Rx buffer. After Reef sends this CC message successfully, it receives
the message the partner sent. So (TCPM) sees an unexpected message was
received, that`s why sends out hard reset.
Root cause:
ANX3429 use a normal R/W register as a interrupt status register.
Between EC read interrupt status and clear interrupt status, if
ANX3429 change interrupt status, it causes interrupt status is
incorrect on EC side.
Solution:
ANX3429 FW use two normal R/W registers for interrupt status reg,
one is for FW interrupt status,other is for EC control register.
Note:
Since cc messages conflict between TCPM and the Partner,ANX3429
shall discard the TCPM message, (TCPM) sometimes send soft reset
depend on the discarded message type.
2. Sometimes TCPM (Reef) does not response GoodCRC for a received mesg.
Root Cause: Reef send message conflict with ANX3429 send auto GoodCRC.
Solution: This is fixed in the 1.5 ANX 3429 firmware.
BUG=chrome-os-partner:53936
BRANCH=none
TEST=On Reef tested with ANX3429 FW v1.5, did not see HARD RST on
ec log with Zinger.
Change-Id: I81da95433e7a0cc71e7ed121b925afccbcd84b06
Signed-off-by: Swang <swang@analogixsemi.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/381014
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added i2ctest console command to test the reliability of the I2C.
By reading/writing to the known registers this tests provides the
number of successful read and writes.
BUG=chrome-os-partner:57487
TEST=Enabled the i2ctest config on Reef and tested the
i2c read/writes.
BRANCH=none
Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290427
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54332
BRANCH=none
TEST=verify only zinger is detected in sink mode (G3/S5), and both
zinger and hoho is detected in dual role mode (S0).
Change-Id: Ifce0009908acc4b1849723ce807ca1b4c8e26020
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387260
Reviewed-by: Shawn N <shawnn@chromium.org>
Add API to switch the Rp pull-up value on CC dynamically at runtime.
This is a preparatory work for boards having a more complex maximum
source current policy (eg 2 ports sharing a common pool of power).
For fusb302, update the voltage thresholds for open/Rd/Ra as they depend
on the Rp (was missing from the previous change).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:56110
TEST=make buildall
Change-Id: Id3c24a31a16217075a398ec21ef58ee07187a882
Reviewed-on: https://chromium-review.googlesource.com/373501
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:54452
TEST=1. To check appropriate register setting.
2. Measure the CC voltage by connecting USB-C to DP cable to EVB.
Default : 433mV
CONFIG_USB_PD_PULLUP_1_5A: 951mV
CONFIG_USB_PD_PULLUP_3A : 1.72V
Change-Id: Id5a36ded94121db4343c48ecea19a5a533244f43
Reviewed-on: https://chromium-review.googlesource.com/371020
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On ANX7688, POWER_STATUS.VBusPresent is averaged 16 times, so its
value may not be set to 1 quickly enough during power role swap.
Therefore, we use a proprietary register to read the unfiltered VBus
value.
BRANCH=oak
BUG=chrome-os-partner:55221
TEST=LG monitor works over type-C, power role swap looks good
Change-Id: I68572c34440be65882f431bb892ed032da05bd0a
Reviewed-on: https://chromium-review.googlesource.com/364351
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Configure the FUSB302 current source used for Rp according to the
CONFIG_USB_PD_PULLUP_xxx value.
Set the default Rp for Kevin to 1.5A.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:54452 chrome-os-partner:56110
TEST=manual: plug to Samus, enable charging on the Samus side,
measure the CC voltage with Twinkie, get 950mV instead of 450mV.
Change-Id: I98faf18132a097e49e9c0fa8e1395d230608ee9e
Reviewed-on: https://chromium-review.googlesource.com/369190
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When disabling auto_good_crc, the reg variable was being used
without initialization. Mirror the code for enabling auto_good_crc
to set the variable.
TEST=Booted reef with updated code.
BUG=None
BRANCH=None
Change-Id: Ie552f2ff74df05750bd65b6344d8a80cc285f8b0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368221
Reviewed-by: David Hendricks <dhendrix@chromium.org>
when the daughter board is not connected, TCPC1 INT# (USB_C1_PD_INT_ODL)
will be floating since the external pull-up is located on the daughter
board as well, and this floating signal will cause an interrupt storm
and eventually cause a watchdog.
BUG=chrome-os-partner:55488
BRANCH=none
TEST=verify board no longer has watchdog reset when daughter baord
is not connected.
Change-Id: If1d73fa7d90f6ac52fd1ab0ac563a6bf5fd10dc0
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365499
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Aux switch settings set the polarity and this happens once on every
cable connect. But when the cable is kept connected if the mux is
set to 0 this is also reset and remains 0 for any next valid mux state.
BRANCH=ToT
BUG=chrome-os-partner:55757
TEST=manual:on reef, plug HDMI type-C dongle and check if DUT screen
is displayed on HDMI display for both the orientation.
Change-Id: Ie1320d11d1927acb292dbaf4c932b48cdfd7768e
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/364693
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously, tcpci_tcpm_set_vconn() would set bit0 and clear all others
of POWER_CTRL. With this patch, only bit0 is updated.
BRANCH=oak
BUG=chrome-os-partner:55221
TEST=plug/unplug apple dongle, check TCPCI 0x1c bit4 should be always 1
Change-Id: I83f113c13bdaad8ce6ece56241296a8f097e1f0a
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360771
Reviewed-by: Todd Broch <tbroch@chromium.org>
The FUSB302A had silicon limitation that required using its
autodetect logic when presenting as a SRC. While testing on
Kevin/Gru and connecting PD dongles, observed issues where
following successful connects, the USB PD state machine would
remain in SRC_DISCONNECTED state after removing the dongle.
Flipping the connector (to reverse polarity) will recover from
this stuck state.
In order to resolve this problem and to make the tcpm_get_cc()
FUSB302 driver function more consistent with the USB PD protocol
state machine while acting as a source, the autodetect feature
is now only used when a revA silicon device is detected.
If it's not revA, then full manual mode is utilized for tcpm_get_cc.
In addition, a new measure_cc_pin_source funciton was added
that consolidates the operations that are shared between both
autodetect and manual modes.
BUG=chrome-os-partner:55429
BRANCH=None
TEST=Manual
Connected display adapter dongles and TypeC hub dongle repeatedly
and verified that each connect attempt resulted in the USB PD
state machine getting to SRC_READY state. Never observed the
error state described above which previously could be repeated
within ~ < 10 connection attempts.
Change-Id: I3c8c6990129e0f1555a6698574adc603d6b7b45b
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361617
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
There was a mistake in the initial driver implementation
regarding the MDAC field in the measure register (address 0x04).
The header file and associated code defined this 6 bit field
to be the upper 6 bits of the 8 bit register. However, the
data sheet for both rev A and B silicon show this field as
being the lower 6 bits of this register.
In addition, when using this threshold to distinguish between
a Rd and Ra attach, the threshold test logic was backwards.
If the threhold bit is set, then it means the voltage is
higher than the 200mV setting and should indicate a Rd attach.
BUG=chrome-os-partner:54790
BRANCH=none
TEST=manual
Tested with Anker TypeC hub using known polarity (CC1). Previously,
would see CC2 be selected as the active polarity. This resulted
in USB PD state machine getting stuck in SRC_DISCOVERY due to
SRC_CAP messages not being received correctly. With the changes,
verified that correct CC polarity is always detected and results
in reaching SRC_READY state.
Change-Id: Ia522abdac31642ff99bbf13ccc73a0a77bbdb32d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361614
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This handles the case where we wish to disable the mux.
Without this the "else" case will return EC_ERROR_UNIMPLEMENTED
when we transition to the PD_STATE_SRC_DISCONNECTED state, and
the EC console shows "Error setting mux port(0)."
BUG=none
BRANCH=none
TEST=no longer see "Error setting mux port(0)" on Reef EC console
Change-Id: I97f35775a5c92636ede1b32293b3a4d01e002dc0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354680
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If set_cc() is called, our toggle interrupt may still be active. Since
alert() is called from the pdcmd task and set_cc() is called from the
pd tasks, an unwanted interrupt may fire and override our desired CC
settings.
BUG=chrome-os-partner:54786
BRANCH=None
TEST=Manual on gru. Rapidly attach + detach DP dongle, verify we don't
get stuck in SNK_DISCONNECTED_DEBOUNCE.
Change-Id: Ib60123c45d9a3a78243a3347377fb2190cbdf94b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356513
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX7688 is a TCPCI compatible port controller with HDMI to DP converter.
The HDMI converter needs a reset every time after enabling its function.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
boot elm proto
plug and unplug dingdong and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/340371
Commit-Ready: Koro Chen <koro.chen@mediatek.com>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
If i2c communication with the TCPC is failing after 300ms+ then it's
likely going to fail forever, so return an error to allow the PD task to
continue initialization.
BUG=chrome-os-partner:53815
BRANCH=None
TEST=Manual on reef. Disconnect TCPC, attach charger to other port, and
verify charge manager correctly sets current limit based on detection.
Change-Id: I2c12320971a77504292f75393791e609e34897b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352501
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Driver implements TCPC for ANX74xx chips. Enables Type C
port for USB and DP alt mode. Enable port role swap feature.
Driver implements TCPC for ANX74xx chips firmware version 1.0 and later.
Please update to ANX74xx firmware to V1.0 or later version to work.
Change list:
1, modify the position of define and struct declare
which response the comment for patch 22.
BUG=chrome-os-partner:49510
BRANCH=none
TEST=tested compiled binary for pdeval-stm32f072 board with this patch.
Power contract establishment, port role swap, DP alt mode works fine.
Change-Id: Iae6322510605a08d3bdd08446116ef5f9e4f7a7c
Signed-off-by: Aman Kumar <akumar@analogixsemi.com>
Signed-off-by: Junhua Xia <jxia@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/322433
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The TCPCI specification defines ane optional register
18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way
of steering the high-speed muxes.
Implement the feature as a usb_mux_driver, under the conditional flag
CONFIG_USB_PD_TCPM_MUX.
The USB PD port index should be set in the port_addr field of the
'usb_mux' structure.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:49605
TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP
muxing.
Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5
Reviewed-on: https://chromium-review.googlesource.com/322956
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add 2 bytes into the TX byte count register used in
TCPC interface.
BUG=chrome-os-partner:48256
BRANCH=none
TEST=load on glados and attach zinger, make sure
PD negotiation successful.
Change-Id: Ie57d79f20def861c22f6e2e023545a65825ab3b4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315879
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Depending on timing, additional important messages may reside on our RX
FIFO at the time we process GoodCRC. Therefore, rather than flushing the
RX FIFO, simply read and discard the GoodCRC message.
BUG=chrome-os-partner:314492
BRANCH=None
TEST=Manual on Snoball with subsequent PWM changes. Verify PD contact
can be established with samus.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4f4fab1bc318d1bce1effffad9a792c5b4a43761
Reviewed-on: https://chromium-review.googlesource.com/314871
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Always initialize TCPC when TCPM boots. This guarantees
that our TCPM driver is synced up with the TCPC reg values.
BUG=chrome-os-partner:47608
BRANCH=none
TEST=test on glados. reboot EC and PD MCUs independently
with and without external power.
Change-Id: I2d989e8a85ba8a72fe1a8edaef8da9c51651d240
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/312951
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a new configuration struct tcpc_config_t that initially defines the
i2c host port and i2c slave address of all TCPCs present on the board.
This will allow us to create boards with multiple TCPCs on different i2c
ports, with arbitrary i2c slave addresses.
BUG=chromium:551078
TEST=Manual on glados. Verify PD communication / charging is still
functional on both PD ports.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9b2bde85d7f1642e8727c052e064371be7967619
Reviewed-on: https://chromium-review.googlesource.com/311000
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Make oak_pd a sym link to glados_pd. A few small changes
necessary to make this possible:
- glados_pd now sets the VBUS present power status bit as oak_pd
does and as is appropriate for TCPCI spec.
- oak_pd now has watchdog enabled (not sure why it was
previously disabled).
- add a flag in gpio.inc to define EC_INT pin on B5 for oak_pd
and A14 for glaods_pd (and all other boards pointing to
glados_pd). Note: this breaks oak board rev 1, where EC_INT was
on A14.
BUG=none
BRANCH=none
TEST=make -j buildall
Load on glados and make sure zinger works.
Change-Id: I28f4ee106e44e2819919f1826508fc1fc05bb2a1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310193
On TCPC startup, set an alert to notify TCPM that we have been
reset. When TCPM gets this notification, it should re-send
initial TCPC parameters. If we were in a stable contract as
a sink, make sure we don't reset connection. If not, then
reset PD protocol state machine to the default state.
This fixes a bug where if the TCPC reboots while the TCPM is
still running, then the TCPC would not get re-initialized and
therefore no PD communication would not work. This also fixes
it such that if we are in a stable contract as a sink and the
TCPC reboots, then we don't lose power.
BUG=chrome-os-partner:46676
BRANCH=none
TEST=tested on glados. reboot PD MCU with and without a charger
plugged in and verify that PD communication works after the
reboot. verify that with a charger, we don't lose power.
also tested with a hoho plugged in during reboot.
Change-Id: I84fec4577b0daf5891bd8461d3f3d925014a5ecf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/307187
Reviewed-by: Shawn N <shawnn@chromium.org>
