Add the Silicon Image sensors, add it to the motion_sense module
to be used with the FIFO.
BRANCH=smaug
TEST=Check light and proxy on Smaug:
Check Light value in Lux are reasonable.
Check Proxy is detecting object, but value are in opposite of distance.
BUG=chrome-os-partner:32829
Change-Id: I11419a0f0613f0fae9323f99deedf5a1e6c6e29c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291335
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add a mask of custom events reserved for IRQ based sensors.
Copy data from raw_xzy to xyz while filling the FIFO
when FIFO is enabled.
BRANCH=smaug
TEST=Test with si1141 driver, check irq works for both driver.
BUG=chrome-os-partner:32829
Change-Id: I5e106df0c121e3bf1385f635195717395235ccc3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291334
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Allow sending calibration information to the magnetometer.
BRANCH=smaug
TEST=Check from user space that calibration is taken into account.
BUG=chrome-os-partner:39900
Change-Id: Ic0f595bde1afdc0b6a79e3516a42b55d1f50c17c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291333
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
This removes a bit of Makefile magic left over from commit
950d507 (April 2013), when we began mocking individual functions
instead of files. It hasn't be used or useful since then.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Iacbef05cb07936f873f29948715e742e1ff465fc
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295175
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Matches definitons set in
chromium/chromeos/accelerometer/accelerometer_types.h.
Using that standard, the coordinate frames of the lid and base DO NOT
line up perfectly when the lid is fully closed or fully open.
Therefore, rotate the lid vector 180 along the X axis before
calculating the lid angle.
BRANCH=cyan
BUG=chrome-os-partner:40177
TEST=When the device is open 180 degrees, check the sensors
agree with each other:
Flat on the back (Z pointing to the sky):
localhost devices # cat */*raw
-1008 [keyboard : X]
-112 [keyboard : Y]
16544 [kyeboard : Z]
-256 [lid : X ]
2000 [lid : Y ]
16336 [lid : Z ]
On the right side (X pointing to the ground)
localhost devices # cat */*raw
-16928
-48
-1040
-16176
432
80
On the bottom edge (Y pointing to the sky)
localhost devices # cat */*raw
-192
15872
1648
496
15936
752
Check the angle as calculated by the EC is correct using accelinfo.
Change-Id: Ib8ee42da8cf818213f892b1f024253f37a4da488
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294716
Reviewed-by: Jonathan Ross <jonross@chromium.org>
Reviewed-by: Eric Caruso <ejcaruso@chromium.org>
On sysjump we attempt to lock all i2c ports in use, but locking is
by-controller. This leads to a deadlock if two ports from the same
controller are in use. Fix this by directly locking all controllers
present in the system.
BUG=chrome-os-partner:44214
TEST=`sysjump rw` and then `sysjump ro` on glados
BRANCH=None
Change-Id: I21d65cd4455769414216016a5c97ad118a712117
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294959
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current logic breaks out of the for() loop if SCL gets unwedged
(goes high), but still falls through to the "I2C unwedge failed,
SCL is being held low" case. Fix this so that we only hit the
"SCL is being held low" case if SCL actually is stuck low.
BUG=none
BRANCH=None
TEST=compile-test only, on samus
Change-Id: I39df1966dc25517ee03a56109e7d0b740c5ca12b
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295043
Reviewed-by: Randall Spangler <rspangler@chromium.org>
PD charger voltage + current can now be limited with
EC_CMD_EXTERNAL_POWER_LIMIT. The limit is automatically cleared when the
AP transitions out of S0 into S3 / suspend.
BUG=chrome-os-partner:43285
TEST=Manual on Samus w/ zinger.
- Plug zinger, verify charging at 20V/3A.
- `ectool extpwrlimit 3000 12000 --dev=1`, verify charging at 12V/3A
- `ectool extpwrlimit 1000 5000 --dev=1`, verify charging at 5V/1A
- Plug zinger into other port, verify still charging at 5V/1A
- `powerd_dbus_suspend`, verify charging at 20V/3A
- `chglim 2000 12000`, verify charging at 12V/2A
- `ectool extpwrlimit 0xffff 0xffff --dev=1`, verify charging at 20V/3A
- `chglim 1000 20000`, verify charging at 20V/1A
- `chglim`, verify charging at 20V/3A
BRANCH=ryu
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6cd5377be91b3df75f99cb414fd3fa5a463b56cb
Reviewed-on: https://chromium-review.googlesource.com/293954
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Some platforms might expect the header of the image to be a certain
platform specific blob. This patch adds an ability to insert an
arbitrary size header in the binary blob, if so desired, the intention
is to have the platform specific tools to postprocess the image and
replace the header with sensible data.
Ideally we should be able to produce an image which is mapped to start
at an offset to the FLASH_BASE, but the macros in ec.S.lds files are
way too smart for this.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with this and other changes the latest cr50 image gets signed and
booted properly.
Change-Id: Icabf00c6b90657b0ae3370ddad3567ccedf3ff49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295200
Reviewed-by: Shawn N <shawnn@chromium.org>
When building components from external libraries, instead of
rsyncing the library into our build directory and building there,
just build in the library directory and have it put its generated
objects into our build tree. That will keep any build artifacts
in the library directory from polluting our builds unexpectedly.
BUG=chrome-os-partner:43025
BRANCH=none
TEST=make buildall
Change-Id: I2f07a2b49d1a0ba9fd9fff0822551486be820b70
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295044
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch closes the loop of processing TPM commands, the response
generated by ExecCommand() is placed in the buffer to be returned
through FIFO read accesses.
State machine and register states are updated as per TCG Platform
Specification. A lot of debug output is generated, this is useful for
debugging, will be filtered eventually.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the appropriate tpm2 and trunks patches in place trunksd
successfully initializes the CR50, sending such commands as
Startup, GetCapability (three times) and SelfTest.
Change-Id: Ibbd952b53930e4530461db7dcdbc510a8022412c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293910
Reviewed-by: Utkarsh Sanghi <usanghi@chromium.org>
The SLEEP_MASK_SPI will not be cleared, if SPI received a bad data.
It is possible to block EC to enter deep sleep if AP send a bad
packet to EC before AP goto S3/S5. In order to ensure that deep
sleep can be enabled, clear SLEEP_MASK_SPI in chipset suspend hook
to avoid this situation.
BUG=chrome-os-partner:44170
BRANCH=None
TEST=manually
1. use AP console command to let AP enter S5:
> shutdown -h now
2. check the sleepmask in EC console.
> sleepmask
sleep mask: 00000000
Change-Id: Ib5f5c421c123d9a3c2cc6fead07c8fa515e452f1
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/294432
Reviewed-by: Rong Chang <rongchang@chromium.org>
Oak board revisions are not global configs. Move them out of
include/config.h . This change also makes it easier to build EC
and PD image for different board revisions.
BRANCH=none
BUG=none
TEST=manual
build for board revision n and load on oak:
make BOARD=oak clean
make BOARD=oak_pd claen
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak -j
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak_pd -j
Change-Id: I331b4c5a1af94b179d7c6f7878a9c3939ea6025a
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294441
Reviewed-by: Shawn N <shawnn@chromium.org>
Oak doesn't have enough interrupt pins to detect VBUS change. This CL
enables oak TCPM power status alert.
BRANCH=none
BUG=chrome-os-partner:41226
BUG=chrome-os-partner:42610
TEST=manual
load on oak rev2. plug in normal type-c charger or legacy type-c
chargers and check charging status.
Change-Id: I9659e749b515f999fe9e81373567f52ec3fe956a
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291161
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Modified TCPC layer to utilize the Power_Status and Power_Status_Mask
registers. VBUS status is stored in Power_Status and when a change
is detected, it's communicated to the TCPM via the ALERT# line.
BUG=chrome-os-partner:43440
BRANCH=none
TEST=Tested the feature on Glados and Oak connecting to both Ziger
and Samus. Verfied that VBUS status is communicated via the TCPCI and
that PD contracts are established without using the VBUS_WAKE GPIO
lines on Glados and Oak.
Change-Id: Ie5aa32eecc887f3cb00880a285f1e710b7064384
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289931
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
BUG=none
TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu.
With only battery after 1 hour, device enters to Pseudo G3 and the
V3p3A is off. With AC connected, device is in G3.
BRANCH=none
Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create a config to allow customization of a board's charger
termination current and add support to bq2589x charger.
Note, BQ2589X_TERM_CURRENT_LIMIT_DEFAULT, currently set to 64 to make
CL benign to ryu board. Future CL will change to 256 as thats the POR
value for that charger.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42848
TEST=manual, read charger IC register and see its termination current
set to 64mA
Change-Id: I79348ed62a077a6432c8d8db6ac90e1e4e92dbc7
Reviewed-on: https://chromium-review.googlesource.com/293095
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Modified i2c driver into controllers and ports to support I2C0 port 0/1 at
the same time.
Modified drivers:
1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions
used by i2c_wedge and i2c_unwedge.
2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func.
3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should
replace GLUE_SDP0/1 with DP80BUF.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/294015
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are a number issues with the current skylake power
sequencing. First, SLP_SUS_L was not being honored from
the chipset when a deep S5 or S3 was requested. Additionally
the BATLOW_L signal was being used to block the chipset from
waking which caused a race in waking from deep S5 that required
an additional pulse of the PCH_WAKE_L signal instead of the
chipset seeing the power button event. Another issue is that
POWER_S5 state was being completely bypassed so any global
resets that brought down SLP_S4_L caused the state machine
to enter into G3 state.
The code was changed to remove BATLOW_L usage, PCH_WAKE_L
in the POWER_G3S5 state, and SLP_SUS_L is honored in the
non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L
pass-thru to work on glaods. Lastly the code was reorganized
to accomodate the above change without sprinkling them
throughout the state transitions.
BUG=chrome-os-partner:44081
BUG=chrome-os-partner:44082
BUG=chrome-os-partner:43475
BRANCH=None
TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh
flash plus a global reset doesn't bring the system down to G3.
Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293844
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The BATLOW_L signal is externally pulled up to PP3300_DSW.
Therefore, there's no need to pull this up internally to
the EC's rail. Additionally, allow BATLOW_L to be high
by default as a forthcoming power sequencing change doesn't
utilize the BATLOW_L signal.
BUG=chrome-os-partner:44081
BUG=chrome-os-partner:44082
BUG=chrome-os-partner:43475
BRANCH=None
TEST=Built and booted glados.
Change-Id: I175408d64b728cacc3f6a305680962fe0320eeb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293843
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The SLP_S0_L signal lives in the primary power well of skylake
while the EC's VCC is on the DSW rail. If SLP_S0_L is pulled up
then there is leakage into the primary well when it's not on.
BUG=chrome-os-partner:44098
BRANCH=None
TEST=Built and booted glados. Default powerindebug state shows SLP_S0_L
low when in deep sleep states.
Change-Id: If9c7972fb6a8b8f90738c1c0f7eea6cf2373d64b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293842
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We will soon have a need to independently set a charge ceiling from both
the PD state machine and from incoming host commands. Store these
ceilings separately, and have the minimum take effect.
BUG=chrome-os-partner:43285
TEST=Pass unit tests. Also, host command current limit takes effect with
subsequent commit.
BRANCH=None
Change-Id: I0ecfe888a7df0d5da5a68999c164c7c841da348b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293818
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The system will not wake from Deep S5 if BATLOW# is asserted,
so wait for that to deassert, then pulse the wake pin and wait
for SLP_SUS_L to deassert.
BUG=chrome-os-partner:43545,chrome-os-partner:44079
BRANCH=none
TEST=verified on P2 board
Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293595
Reviewed-by: Shawn N <shawnn@chromium.org>
The SPS RX FIFO handler prototype changed from passing cs_enabled
to cs_disabled, but the callback function for the spshc command didn't.
Now it does.
The spshc command switches the protocol on the SPI Slave bus to
expect EC Host Commands.
BUG=none
BRANCH=none
TEST=manual
At the EC console:
spstpm off
spshc
On the build machine, with an FTDI cable connected to the SPS
input:
cd extra/ftdi_hostcmd
make
./test_cmds
Change-Id: I69294a977b83854c5f6348904330bf74416cc6ec
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293619
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Switch to V2 glados as the default, and remove support for V1.
BUG=chrome-os-partner:43075
TEST=`make buildall -j`
BRANCH=None
Change-Id: I58f33225177d259916e8877084c2c431922e7bc5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch syncs up TPM2 sources into the build area when building
cr50 image. This relies on a specific directory layout so that the ec
makefile has access to the tpm2 source tree.
The sources are copied using rsync, the tpm2 library is a dependency
for the RO/RW elf images, and is declared to be a phony make target,
which guarantees that the tpm2 make is always run when cr50 image is
built.
Include files in board/cr50/tpm2 are necessary to be able to build
tpm2 code using the bare metal toolchain used for building ec code.
memory.h is in fact empty, it is easier to add it here than to wrap it
in conditional compilation at the source.
Make variables CROSS_COMPILE and CFLAGS are exported for the benefit
of the tpm2 makefile. ROOTDIR indicates where tpm2 library should look
for .h files not available from the toolchain.
CQ-DEPEND=CL:292946
BRANCH=none
BUG=chrome-os-partner:43025
TEST=make buildall -j succeeds;
when linked with the latest tpm2 source, the combined image
starts the tmp task and reacts to the host sending the startup
command (failing due to unplugged stubs).
Change-Id: Ia3fd260588558c2bacd724df9583052fa4660ca3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292975
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
TPM command processing should not be happening on the interrupt
context.
This patch adds a skeleton of the task which handles TPM functions. It
initializes the TPM and then enters endless loop waiting for an event
trigger from interrupt, which happens when a valid FIFO message is
received.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=none yet
Change-Id: I63dce2762cc07370a05bf00bdf144c5d9eb6019b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289332
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
symptom:
Enable debugging and profiling statistics for hook functions
(#define CONFIG_HOOK_DEBUG), and __muldi3 function is missing
while link.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. compile successful and hook_notify starting to print message.
2. console "hookstats"
Change-Id: Ia2815bcefd0f9ac06dab9c75ea6ee06312878ca2
Reviewed-on: https://chromium-review.googlesource.com/293432
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
bug: when typing
> tw bufrd 3 2
in twinkie console, the command will output 3 elements
However, the third argument(3) is where it starts output
the elements; and the fourth argument(2) is the number
of elements to be printed.
Original code uses: "cnt = strtoi(argv[0], &e, 10);" to
get the count.
It should use "cnt = strtoi(argv[1], &e, 10);" instead.
Signed-off-by: Dawei Li <daweili@google.com>
Change-Id: I04cf041e47cdf72c5189e4b8446c8f8e4cc5e2e5
Reviewed-on: https://chromium-review.googlesource.com/293561
Tested-by: Dawei Li <daweili@google.com>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Commit-Queue: Sheng-liang Song <ssl@chromium.org>
The default receive FIFO threshold of 8 (meaning that 9 bytes need to
be received before receive IRQ fires) is good for high volume
transfers, when the amount of transferred data greatly exceeds the
threshold.
But in case of TPM transactions, which start with a 4 byte header and
then stall while the device processes it, the default threshold
guarantees delays on every transaction, as the receiver does not start
processing the header until 5 idle bytes are transferred to bring the
total number to nine.
The suggested solution is to allow to specify the receive FIFO
interrupt request threshold at run time, by adding this value to the
receive function registration API.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that spstest still works fine.
Change-Id: I92517205a7d0d47893b702efa188eb524fb18a49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289331
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
With the recent changes to the build system, RW objects are located in
the RW/ subdirectory of the output build directory. This commit fixes
the build for the variant.
BRANCH=None
BUG=chrome-os-partner:43965
TEST=./board/twinkie/build_rw_variant; build is successful.
Change-Id: Ifab1994e6e368cc61784df7358c59b7ebd87e67c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/293344
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Dawei Li <daweili@google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
npcx GPIO code calls out to an LPC function, which isn't defined on
platforms without LPC support.
BUG=chromium:520207
TEST=`make buildall -j`
BRANCH=None
Change-Id: I80c0d08fea4a2621df9646926959fc48af52a15a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293013
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- PMIC init can be called from HOOK_INIT now that this happens after the
scheduler has started.
- There's no need to re-initialize the PMIC on sysjump
BUG=None
TEST=Verify glados boots to S0
BRANCH=None
Change-Id: I1839e1bd357759ae2800d812b27bf4e0cd7772b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293012
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we have a lightbar, but no PD, then plugging the device in will
not trigger the battery-level pattern. This allows us to trigger
it from the charger task instead if we change AC status and don't
have a PD.
BRANCH=ToT
BUG=None
TEST=plug and unplug charger from device, make sure the lightbar
plays the right pattern
Change-Id: I8f37aaff2ddb9d936e13489cb404caee822418a1
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292943
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The glados_pd test build runs out of RAM, so disable it for now.
BUG=chrome-os-partner:43948
TEST=emerge-glados chromeos-ec
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I519917a36d193931e993cf16487ac33c81ceb163
Reviewed-on: https://chromium-review.googlesource.com/292935
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fixed bug during polling port 0x204 by BIOS.
We should set processing flag before reading command byte in ISR to prevent
EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low.
Modified drivers:
1. gpio.c: Add LRESET ISR.
2. lpc.c: Fixed bug during polling port 0x204 by BIOS.
3. flash_ec: Reset ec before flashing ec
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/291210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Symbolic link kunimitsu_pd to glados_pd folder. Disable PD test
build until issue is fixed.
BUG=chrome-os-partner:43142
TEST=emerge-kunimitsu chromeos-ec and check EC and PD binaries
Change-Id: Ic0f1d73246333d8ec7752bb4c42b1c0ac220b5c3
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292841
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
`tests` build was previously disabled for glados due to errors building
power/skylake.c. Properly undef the chipset config to make `tests` work
for all skylake platforms.
BUG=None
TEST=`make BOARD=glados tests`
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7a730cdd5e30a932ff0cd1f3beef77873b9e0630
Reviewed-on: https://chromium-review.googlesource.com/292910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The public sources look for board configurations in directories
named board/$BOARD/
Sometimes it's necessary to keep sensitive projects out of the
public view for a bit.
This CL allows board configurations to also appear in directories
named private*/board/$BOARD/
BUG=none
BRANCH=none
TEST=manual
First, ebuilds and "make buildall" seem to work just as before.
Second, I copied 24 of the existing boards (those without
board-specific #ifdefs in the code) into a private*/board/
directory, renamed them to something unique, and ran "make
buildall" again.
Both public and private boards compiled and passed their tests.
Change-Id: I977c23cb8e73e40677c8f329abca8bbc51fd53df
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Use new board-level hibernate GPIO state function to turn off LEDs in
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id695df9b5e75514f8f807a894b63f71676b66f92
Reviewed-on: https://chromium-review.googlesource.com/292317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
