AmdS3Save no longer exists in Carrizo.
Imc lib should move to southbridge.
Change-Id: I2c925adf4469bb53139abe48108800655db2a5fe
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
It's already defined in stdint.h and redefining it here conflicts
with coreboot proper.
Change-Id: I9a250b37b2f39278e4fdcd5c4b094457394549b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the microcde from chromium.org commit:
584219ff73ea4888995f460d2292b1b236f62c28
Change-Id: I87224206436a500e042215a844f0a8d8c042382a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Picked up from chromium.org commit:
1b2f4ca558c29b3bb5b8eb9b7d935ddf84d222ee
Change-Id: If597662cce66ff8937a6d310ecdf2bd849e258f2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Add AGESA BLOB, head files, VBIOS, xHCI, IMC and PSP firmwares
into the 3rdparty repo. These are explicitly to support AMD
Embedded "Merlin Falcon" processors in a FP4 package.
I have tested on board Bettong. Windows 7, Windows 8 and
Ubuntu 14.04 can boot.
Change-Id: I61abc61b0a837eb1e7b9bee6f6155f92d6c7419d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
The AGESA.c file in 3rdparty has cbfs access functions
for locating the AGESA binaries. coreboot access functions
need to be within coreboot where they can be updated with
cbfs changes. Move the offending function to coreboot.
Change-Id: Ic414d2c74e270548d5190e8c95e4cd7b8f3b8edd
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
The fake binaries *.mbn need an 8 byte header
d1 dc 4b 84 34 10 d7 73 for mbncat.py to accept them.
Add all files that will be needed for IPQ806x builds
down the line.
This will still not produce a working coreboot binary, but
it will fix compilation of coreboot.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I8cbb45eeb559f673deeefbf7692aff6b0211e59f
Please update uber-sbl.mbn from your existing coreboot image.
These are only dummy images to make the build pass.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I20be2c7c71fcad274c7ef281f430f090b282e9ee
Add the microcode to 3rdparty blobs repository. These are
direct copies from the coreboot repository.
Change-Id: I25476addd5f507420a1e89ae6d60264312a15038
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Add the microcode to 3rdparty blobs repository. These are direct
copies from the coreboot repository.
Change-Id: I042e5454eabe4d4ae636932cc516e9e5ff3d4d53
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
AGESA ENHANCEMENTS and FIXED BUGS after 1.0.0.4:
- Fixed ECC issue
- VRM values compatible with 53081 Rev. 1.03
Known Issues/Limitations:
- Warm boot times may exceed cold boot times
(affects ADK Fast Boot results)
- fTPM and DASH are not yet fully implemented
TEST:
Boot win7/8,ubuntu OS on Olive Hill+ board successfully
Verify that single ECC DIMM failure is gone
Change-Id: I88b2c4bdeb6b638218a2d2935da6ad35a1f5dc0a
Signed-off-by: William Wang <william.wang@amd.com>
Signed-off-by: William Wang <william20140704@yahoo.com>
This is done by creating a model_306ax dir. The update-microcodes
script will then automatically extract the relevant microcode.
Change-Id: Idf78088b58ad2ce9dc9e6881adf3a8ee9d2fd03c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Microcode files will need to be added to this repository before they
can be removed from the main coreboot repo. Add them in anticipation
of this change. The script was updated to pull the latest microcode.
These files were extracted using the update-microcodes.sh script, and
may not necessarily match the updates currently present in the main
repository.
Change-Id: I30d41ff31b1ebb6aaeb773c2c663d7176d27060d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Rather than simply extracting the microcode updates, also create a
microcode.h header for each model, to include the extracted microcode
updates.
This should make maintenance easier, as coreboot code will be able to
simply include the "microcode.h" files in 3dparty rather than having
to update the includes every time the microcodes are updated in here.
Change-Id: I7abd81f984b1a61aeb6041d85b366e9a45c59421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Agesa ENHANCEMENTS and FIXED BUGS after 1.1.0.5:
- BUG: Quad limited to Dual, XHCI controllers will disappear after r
- ENH: FCH - POST API for GPIO definition
- ENH: Reduce padding size for SMU firmware
- BUG: Pcie Training Hangs on Broken Line failure
- BUG: GNB IOAPIC devid in IVRS table should be 0:0:1
- ENH: Kaveri SMU Firmware 13.52.0
- BUG: Clear EcPortActive if IMC is disabled
- BUG: Name string in Core 2 mismatch BSP setting
- ENH: AGESA FCH USB EHCI Deep Blink Power Saving changes
- BUG: eDP does not light up
- BUG: BTS Shows warnings on several registers
- ENH: KV Gen3 EQ CMOS Default Settings Changes
- BUG: Wrong Timing parameters passed to PMU Message Block in mixed
- ENH: Brand String Updates for Server and Embedded
- ENH: Update NFC reference driver on KV as test result on KV platfo
===========================================================================
Additional changes that are specific to coreboot:
---------------------------------------------------------------------------
KaveriPI: Updates the IMC code to v1.1.2
Since existing Trinity/Richland and Ontario boards use the v1.1.1
code stored in southbridge/amd/hudson, move the Hudson v1.1.2 IMC
binary from this update to KaveriPI under southbridge/amd/bolton.
This is a potential problem for future KaveriPI updates since the
path is changed from the AMD conventions used for KaveriPI.
Technically, all discrete FCH designs (Kaveri, Trinity/Richland,
Ontario, possibly Orochi) should use the latest Hudson IMC code.
KavariPi: Change licensing on gcc-intrin.h per Palamida scan
Palamida scan run on behalf of AMD found that the source license
for gcc-intrin.h should be attributed to hackbunny@reactos.com.
License was restored to the original KJK:Hyperion text.
===========================================================================
Change-Id: Ie5ef48671ad4adab835ee6cba1dcafc4e12c18ee
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.3:
- ENH: FCH - POST API for GPIO definition
- BUG: Pcie Training Hangs on Broken Line failure
- ENH: Save Restore FakeSMI related registers for S3
- BUG: AGESA-FCH Can't set SPI Dual_122 mode
- BUG: EHCI driven strength programming is not consistent with BKDG
- BUG: D18F2x9C_x0D0F_0[F,8:0]04[POdtOff] fails to be maintained
- ENH: PSP FW Stack (Mullins-Beema) version D.1.1.22
- ENH: Mullins_Firmware_14_31_0
- ENH: Sensor feature is not working
- BUG: Potential Stack contaminate during TPM memory ready callback
- ENH: ALIB skip training on hot unplug
- ENH: PSP FW Stack (Mullins) version 0.1.1.1E
- ENH: AGESA enhancement to implement workaround for ERRATA 793
Known Issues/Limitations
- Warm boot times may exceed cold boot times (affects ADK Fast Boot results)
- fTPM and DASH are not yet fully implemented
======================================================================
Additional changes that are specific to the AGESA binary for coreboot:
----------------------------------------------------------------------
MullinsPI: Change licensing on gcc-intrin.h per Palamida scan
Palamida scan run on behalf of AMD found that the source license
for gcc-intrin.h should be attributed to hackbunny@reactos.com.
License was restored to the original KJK:Hyperion text.
MullinsPI: Disable quad rank support
Mullins does not support quad rank DIMMs. Turning this off
allows both DIMMs to be detected on a olivehillplus.
Mullins: GfxInitSview() needs to preserve GFX PCI config space
The GfxInitSview() exits with the I/O decode disabled in the
GFX (BDF=0:1.0) PCI config space. This commit copies the
algorithm used for Trinity.
MullinsPI: Prevent SPI Quad I/O mode from being used
The AGESA code for SPI Quad I/O mode has multiple problems.
These problems were first observed on the amd/DB-FT3b-LC board
which has a SPI rom that supports quad I/O mode.
In the function FchPlatformSpiQe() it is not able to correctly
detect the QeEnabled bit to determine if quad mode should be
turned on. This results in the function FchSetSpi() erasing
the sector where the hudson/fwm header is stored and as a
result the motherboard will not be able to be rebooted.
MullinsPI: Turn on IOMMU
The IOMMU cannot be turned on from coreboot if the IOMMU flag is
set "OFF" in binary PI. This is because turning off IOMMU in
build options disables compilation of the code that generates
the IVRS ACPI table. Turning on the IOMMU flag should have no
effect in coreboot code unless the IOMMU is explicitly enabled
before the call to AMD_INIT_ENV.
MullinsPI: Eliminate BOUNDS_CHK errors for HEAP locate objects function
The HEAP locate objects function is frequently used in AGESA to test
whether code has already run. This results in an AGESA BOUNDS_CHK
error being reported and the subsequent logging of the error. These
are not errors and they either cause a lot of work to revisit whether
they are valid or all BOUNDS_CHK errors get ignored through invalid
use of the error. Remove the reporting of BOUNDS_CHK errors within
the HEAP locate buffer function.
======================================================================
Change-Id: Id45be29a330089e86a55bdd4571538fe43ea7668
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
The Azalia table is a lookup. It is hard to imagine that it should
not be CONST. The compiler does not complain when the Azalia
related fields in the structs passed into the AGESA OEM callout
are set CONST. If the compiler does not complain, then the
calling function does not modify the Azalia lookup table.
Therefore, there is no issue with setting the Azalia verb table
pointer fields as CONST. All this does is provide more detail to the
compiler so that it can flag errors at compile-time rather than
runtime.
Change-Id: I269c137f8644e97e095e1e39df1a255223cf07b0
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
KavariPi: Change the default Sata6AhciCap to TRUE
Change an internal AGESA variable to allow SATA AHCI
mode to grab all six ports
KaveriPI: Eliminate BOUNDS_CHK errors for HEAP locate objects function
Internal to AGESA, HEAP locate functions return an
error code. The error code shows up in the output from
AmdReadEventLog(). Sometimes the locate functions are
only used to determine if processing has already occurred.
Change AGESA so that no error is generated in the log
for simple locates. Memory allocates and deallocates
still generate an error.
Kaveri: GfxInitSview() needs to preserve GFX PCI config space
When GfxInitSview() starts processing, it sets the I/O,
memory, and busmaster bits in the integrated graphics device
config space header. When GfxInitSview() completes the
I/O bit is cleared. Change AGESA so that GfxInitSview()
preserves the config space I/O, memory, and busmaster
bits through the function.
Change-Id: Ic30afefa9e0da14017642e1242976771908847bc
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Add the header files, Makefiles, and Kconfig files to support the
AMD Embedded "Bald Eagle" binary AGESA. The header files need to
exactly match the files used to build binary AGESA.
Change-Id: I7a245bc4d36faa65838f3f41d2367889531d9aa7
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Move the Bald Eagle AGESA.bin file into a socket-specific directory
to highlight that this BLOB is only for soldered down processors in
an FP3 package.
Change-Id: Iabef48c2f64a5d1fd7c1a9b1de65460308165f0c
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
**************************************************************************
* ATTENTION: The blobs/cpu/qualcomm/ipq8064/sbls.bin file is a
* placeholder.
* It is NOT a working IPQ8064 binary.
*
* Developers should maintain the IPQ8064 file on the flash device and be
* sure to back it up prior to overwriting it with a coreboot image.
**************************************************************************
Change-Id: Ifadede6d7851a7dfb2eada8f58752a5971f9a9aa
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Steppe Eagle (00730F01) contains the Avalon southbridge and
a Platform Security Processor (PSP). Supporting the PSP requires
specific binaries to be included in the rom. These binaries are
being added to the AMD directory as separate pieces but will be
swapped out for a combined binary in the future. The fletcher
utility is used to sign PSP binaries.
Change-Id: If6325d5f9ecec141317436a602c4cc1349a3f13f
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Add the header files, Makefiles, and Kconfig files to support the
AMD Embedded "Steppe Eagle" binary AGESA. The header files need to
exactly the files used to build binary AGESA.
Change-Id: Ia81caaaa3d90a3c23280a06fcfb50b922c94288a
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Move the Steppe Eagle AGESA.bin file into a socket-specific directory
to highlight that this BLOB is only for soldered down processors in
an FT3b package.
Change-Id: I291b6a60be7d8f9d784e75650bc721495d89a4c7
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Move the AGESA BLOB from the CPU directory to the PI directory to match
the organization of the Steppe Eagle directory. Convert the license
file from RTF to text so that it can be reviewed in Gerrit.
Change-Id: I2b7e499ea458939af3ed5bf4e4e8d59301733ffc
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Add AGESA BLOB, VBIOS, and xHCI BLOB into the 3rdparty repo. These
are explicitly to support AMD Embedded "Steppe Eagle" processors in
an FT3b package. These BLOBs may also work with other AMD Mullins
based processors but use with other variants is not supported.
Change-Id: I6911e03fc605d38cf8283d34113ae8943ffa2500
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
- Update the imc.bin file to v1.0.11
- Add the imc.bin release notes
- These files are released under the license file
added in the xhci binary file update - commit 5cb8acef.
These files were obtained from:
RichlandPI_1.1.0.5 - April 2014
Change-Id: I5dbb97d9cd767bde98028645a4b14b5cc68526ea
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
- Add the updated xhci binary - Version 1.0.0.48
- Add the release notes for the xhci binary
- Add AMD's license file.
These files were obtained from:
RichlandPI_1.1.0.5 - April 2014
Change-Id: Id4ab7bb09b203b8afe7250b78c36012b6735f4b2
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Add AGESA BLOB, VBIOS, and xHCI BLOB into the 3rdparty repo. These
are explicitly to support AMD Embedded "Bald Eagle" processors in
an FP3 package. These BLOBs may also work with other AMD Kaveri
based processor but use with other Kaveris is not supported and has
not been tested. Use at your own risk.
Change-Id: Ia3807835fdde3b2ee76ab25cfa7943085866d794
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Add the update-microcodes.sh script in anticipation of removing the
microcode updates from the main coreboot repository.
The script is copied verbatim from main repository.
Change-Id: I4d07d48646d71d58b5be329a24352ec04ae2f02d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The code tests a register 5000 times that I doubt exists
on sandy bridge. reduce to 50.
Change-Id: I86d0e35e3a8cd61b3f7c531cd4e3dd8cc5b28f57
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
This is a fake binary. Run strings on it to determine the
URL of the real binary.
Change-Id: Iaebdb2336e1df3b10395031b8f19d46b7550acc6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
The pei_data version changed to 6, so new binaries are needed.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia4f85c12d11d89a17c38530b1d92861d1cdad679
Look into the file to find out where to get the actual bootblock
for now. This is hopefully temporary to get the coreboot build process
in place and working.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I53987a0515b00af83f959468296b4c5929ba49df
The pei_data version changed, so new binaries are needed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ic7f503f5ad547c9268b50b356b2835a7677319e1
