There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup.
Without the internal pull up SYS_RST_ODL is asserted when the EC is off.
This change modifies how sys_rst_asserted is handled so cr50 will ignore
the sys_rst interrupt whenever rbox asserts EC_RST to make sure cr50
doesn't reset itself every time it resets the EC. If the EC resets
itself and sys_rst_l is no longer pulled up, it is fine if cr50 resets.
BUG=chrome-os-partner:53544
CQ-DEPEND=CL:377504
BRANCH=none
TEST=manual
'rw 0x40550010 1' causes the EC to reset but not cr50
On the development board verify DIOM0 is not pulled up.
Test cr50 boots normally on reef, gru and kevin dvt1
Change-Id: Id8e8f6f7bb91741da34bdd6fec89eb841dd94f35
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376886
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On boards using cr50 as the TPM there needs to be a pullup on SYS_RST_L
BUG=chrome-os-partner:56701
BRANCH=none
TEST=verify SYS_RST_L is pulled up on DVT1 and earlier.
Change-Id: Ib87ef48bafe1dad1329678f9a80c34c7adc2df01
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377504
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to disable the restricted console lock, the user has to
poke the power button repeatedly for some time. This CL
implements the logic to tell when this is happening, and whether
it is successful or not.
With this CL, unlocking only takes 10 seconds. This period will
be extended for production use. Right now we're just testing.
BUG=chrome-os-partner:55322
BUG=chrome-os-partner:55510
BRANCH=none
TEST=make buildall; test on cr50 hardware
At the console, run the "lock" command to see if it's already
disabled. If it is, run "lock enable" to lock it.
To unlock it, run "lock disable". A countdown will appear, after
which you will need to poke the Power button every 2 seconds for
10 seconds. If you do so, the console will be unlocked.
Change-Id: Ib5a94172080e627f3268d50d2587ec58bf8d9473
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377621
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This enables restricted console commands, meaning that only the
"help" command would be available when the Cr50 console is locked.
To get out of (or into) the locked state, this also adds a "lock"
command. Of course, it will be available in locked mode.
For now, the lock state is disabled, so all commands continue to
work as before. Even after enabling the lock, it's trivial to
disable it again. Future CLs will build on this framework.
BUG=chrome-os-partner:55322,chrome-os-partner:55510
BRANCH=none
TEST=make buildall, test on Cr50 hardware
Try these commands:
lock
help
gpioget
lock enable
help
gpioget
lock disable
help
gpioget
Change-Id: I42c9bd63e17612dcff78c9f45054e53d96adcd5b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376187
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit adds a board level hibernate call which will place both of
the TCPCs into a low power state. When the EC wakes up from hibernate,
we will reinitialise the TCPCs back to full power.
BUG=chrome-os-partner:55631
BRANCH=None
TEST=make -j buildall
TEST=Flash kevin; Boot up, shutdown. Enter `hibernate` at the console.
Verify G3 power is less than prior to this patch.
Change-Id: I9d71495358c16268352bf3820318ec151836c5de
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/376864
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting the higher limit of input current for BC1.2 & nonstandard
BC1.2 devices than their maximum current rating results in an
anti-collapse. BD99955 does not have a way to do hardware charge
ramp or to detect the anti-collapse for these chargers. Hence added
code to support software charge ramp for BC1.2 & nonstandard BC1.2
so that the input current is set to maximum of the respective
charger.
BUG=chrome-os-partner:54990, chrome-os-partner:55517
BRANCH=none
TEST=Manually tested on Amenia & Reef. BC1.2 & nonstandard BC12
devices can negotiate their respective maximum current rating.
Change-Id: I0033b3662362bd7822ad01cf4360d18caabd5249
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/358106
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Set the EC_WIRELESS_SWITCH flags in Board file. This signals the
common code to maintain the ON or OFF state of the power rails for
the Wifi/Bluetooth chip when chipset enters suspend state.
BUG=chrome-os-partner:56305
BRANCH=none
TEST=Boot the system with a Bluetooth Mouse paired. Open a Linux
shell and type powerd_dbus_suspend. When the system enters
sleep state, click the mouse. System should wake up.
Change-Id: I261ca03d34bc8a05d3a2aa5fcb777f714fe30572
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/374164
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Addition to 4523735d: We can use the BMI160 internal FIFO, so set only
the Lid accel in forced mode.
Set EC rate for BMI160 accel as needed.
BRANCH=kevin
BUG=b:27849483
TEST=Check sensor parameters with accelrate. Check rotation is working.
Change-Id: I86f50e019db25837894036c4f27b255a65d2f894
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add API to switch the Rp pull-up value on CC dynamically at runtime.
This is a preparatory work for boards having a more complex maximum
source current policy (eg 2 ports sharing a common pool of power).
For fusb302, update the voltage thresholds for open/Rd/Ra as they depend
on the Rp (was missing from the previous change).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:56110
TEST=make buildall
Change-Id: Id3c24a31a16217075a398ec21ef58ee07187a882
Reviewed-on: https://chromium-review.googlesource.com/373501
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cr50 needs to connect to the AP phy when not in ccd so cr50 can be
updated and used as a gnubby. This change uses the strapping options
to detect when it is on reef and modifies the ccd behavior to
initialize usb on the AP phy when ccd is disabled. On gru the cr50
behavior is unchanged.
In RDD this change removes the checks that the current_map is the
correct one based on the detected debug state. rdd_init calls
rdd_interrupt to set up the usb and ccd state correctly. Having that
check prevents that initial rdd_interrupt from calling rdd_detached.
Before rdd_detached just disabled usb and we knew during init it
would already be disabled. Now we want to make sure it is called if a
debug accessory is not attached to initialize usb on the AP PHY.
BUG=chrome-os-partner:56098
BRANCH=none
TEST=manual
verify ccd still works on gru
disconnect suzyq and reset reef.
run lsusb on the AP and verify it shows cr50 as a device.
connect suzyq and check that the AP no longer sees cr50.
disconnect suzyq and verify the AP sees it again
Change-Id: I3c1ccc54895835bce12302f3ea43fc2e751b4c97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372920
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add tests for CBC, CFB and OFB AES modes.
Also convert tests to use word unligned
input parameters, to ensure that the api's
are unalignment agnostic.
Also add the program used for generating
test vectors.
BRANCH=none
BUG=chrome-os-partner:56413
TEST=tpmtest.py passes
Change-Id: I92c9ffece797aa7134d9cdad6ea32e6fe50feef1
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/374663
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
when TCPC takes a longer time to update its CC status upon
connection, a legacy C-to-A charger or certain Type-C charger
that presents 5V VBUS by default, TCPM could be mistaken the
charger as a debug accessory.
BUG=chrome-os-partner:55980
BRANCH=none
TEST=Manually tested on Reef. PD, Type-C, BC1.2, non-BC1.2,
DP, HDMI are working on both C-ports.
Change-Id: Ic3b0ecd3d14109239d8c0ff0064476595b7f93a0
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/367950
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Due to what appaers to be a leakage issue, this patch drives the
SYS_RST_ODL (aka PMU_RSTBTN_N) pin low for 1sec while the power
state transitions from S3 to S0.
This is a workaround for a proto board issue that prevents the SoC
from booting.
BUG=chrome-os-partner:53791
BRANCH=none
TEST=SoC boots with CL:347754 applied on proto and EVT boards
Change-Id: I88c3ccf18280acf5dfe3b99f99483dc4e4e27873
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372044
Reviewed-by: Martin Roth <martinroth@chromium.org>
This changes the ordering of rail/PMIC init slightly so that the
3.3V rail comes up before the PMIC, which follows the ordering
in the PMIC datasheet for cold booting.
The way we did it earlier was to avoid interrupt storms caused by
powering the SoC's GPIO block with SLP signals before powering the
PMIC. However the PMIC ignores the SLP signals when it's first
enabled, so while the suprious interrupts were visible on the scope
it's unlikely that the software was affected. OTOH, as Kevin pointed
out in CL:358913 enabling the PMIC before the 3.3V causes a race
condition whereby the PMIC may fault.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=built and booted on EVT
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I6eb734f0600daa5de0d970ce228cf3e7ec97d01d
Reviewed-on: https://chromium-review.googlesource.com/372344
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the charger is detached, the host event would sometimes be
sent before the charge info was updated, resulting in the host
thinking that the charger was still connected.
BUG=chrome-os-partner:55584
BRANCH=none
TEST=Connected charger to kevin 15 times and verified that the
icon was removed in 2-seconds or less.
Change-Id: I1a4e4e0f7cc23010210570fc261da8308d8e8070
Reviewed-on: https://chromium-review.googlesource.com/367809
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
BMP280 driver API is designed to work with motion
sensor task. The sensor sampling parameters are
configured optimally for handheld device in accordance
with BMP280 spec recommendation.
BUG=None
BRANCH=master
TEST=Tested on amenia; with appropriate .odr in board file
test command "accelread 4" returns raw pressure
value in Pa; accelinfo on 4000 shows Pa value.
Change-Id: I3f4c0c33a77dd317aa1425624d3cc7f4ec6b45a1
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351660
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Do not power-on the AP unless battery can provide sufficient power
or the charger is negotiated to sufficient power.
BUG=chrome-os-partner:56494
BRANCH=none
TEST=Manually tested on Reef. Device can boot to OS without the
battery & cut-off battery.
Change-Id: Ib22bad81a29ccbb2fecc8e835148b627dd722988
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/374023
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Sensor FIFO, set the sensors in force mode since we haven't enabled
their FIFO.
BRANCH=kevin
BUG=b:27849483
TEST=Check kernel load cros-ec-ring.
Check ARC++ get accel info with AIDA64.
Change-Id: I1c4d5c1291d2c778fdabd8b8f4e6b6a370f37b04
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373140
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When SW sync is enabled and the board enters G3 after being up
there was no way to boot the board again because the
system_jumped_to_this_image() check disallowed the pmic startup
sequence. One needs to check if the pmic is also already on
before bailing on the pmic startup sequence.
BUG=chrome-os-partner:56530
BRANCH=None
TEST=Booted. Jumped to RW EC. Shutdown system. Can boot again once
G3 entered.
Change-Id: I71670ceee09536a282479d1eca6a3ce264f0f5d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374080
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup.
Without the internal pull up SYS_RST_ODL is not pulled up whenever the
EC is off. I changed how sys_rst_asserted is handled so it will ignore
the sys_rst interrupt whenever rbox asserts EC_RST to make sure cr50
doesn't reset itself every time it resets the EC. If the EC resets
itself and sys_rst_l is no longer pulled up, it is fine if cr50 resets.
BUG=chrome-os-partner:53544
BRANCH=none
TEST=manual
'rw 0x40550010 1' causes the EC to reset but not cr50
On the development board verify DIOM0 is not pulled up.
Test cr50 boots normally on reef and gru
Change-Id: Ic1d4d160ddb0d69081cb1f194d50939dac6fc5c2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373838
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
GPIO interrupts must first be enabled with a call to
gpio_enable_interrupt() to prevent ISRs from being run before
prerequiste modules are initialized.
BUG=chrome-os-partner:56486
BRANCH=None
TEST=Manual on kevin, stress test sysjump for ~1 hour (~700 sysjumps)
without failure.
Change-Id: Ia4006ef1b0c3218dfe5c92fde6713c10b0d22d2a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374020
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
We have enough memory for that, and it makes it possible to poll the
logs from AP much more unfrequently.
BRANCH=none
BUG=chrome-os-partner:56460
TEST=make buildall -j
TEST=Boot kevin, cat /sys/kernel/debug/cros_ec/console_log does not
miss any data.
Change-Id: I7dc880a27d34f97746a8fde00e49d8d08ed85b9d
Reviewed-on: https://chromium-review.googlesource.com/373285
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The parse_bool() function exists so we don't have to litter our
console commands with stuff like this:
if (!strncasecmp(argv[1], "on") ||
!strncasecmp(argv[1], "enable" ||
!strncasecmp(argv[1], "true" ||
[...]
This CL uses parse_bool instead of that kind of thing so I don't
have to remember which commands use "enable" and which use "on"
and so forth.
I only changed the commands that Cr50 uses.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
I tested all the affected commands to ensure that they still work
correctly: usb, ccd, flashwp (which doesn't do anything anyway).
Change-Id: I7d875ab22934fb4b500e3d0f62ebe3e04101272d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373658
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:49959
BRANCH=none
TEST=manual
On the Cr50 console, use the "wp" command to get/set the desired
state. On the EC console, use "gpioget wp_l" to watch it change.
Change-Id: I5978e6116ad0a07a7a61a8356dc1daf79e2397d0
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373618
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This command was used for early testing of the SPI slave
interface. It's no longer needed, so disable it to save space.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: If730f909c7361b1179e23b2bf1d07c9d51aa6e8f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373619
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Display backlight going down for an extended period of time is
a major user annoyance, so save the duty prior to sysjump and restore it
upon init.
BUG=chrome-os-partner:56390
BRANCH=None
TEST=On kevin, run "sysjump rw" from recovery screen, verify backlight
goes black for a fraction of a second and comes back to previous level.
Change-Id: I98f12ace9b933874ba9088a790b9efa0941050ed
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373621
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
kevin EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms. Even when hcdebug is set to off, we still
get command errors.
BRANCH=none
BUG=chrome-os-partner:56460
TEST=make buildall -j
TEST=Flash kevin EC, see that output is fairly quiet.
Change-Id: Iad974c463c8dd91960e872ec977fe0e653696701
Reviewed-on: https://chromium-review.googlesource.com/373284
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With "ectool led power blue=0 green=100 red=100", LED color is changed.
But LED will turn off immediately.
To keep color with "ectool led", we need remove led turn off when
"Battery/Power LED" auto control are not enabled.
BUG=chrome-os-partner:56179
BRANCH=none
TEST=manual, run ectool command on user space.
ectool led power blue=0 red=100 green=100
ectool led power blue=100 red=0 green=100
ectool led power blue=100 red=100 green=0
ectool led power auto
Change-Id: Ifa6b426443ca800f34ba7c61cea6e2e49694fb0e
Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/368586
Reviewed-by: Shawn N <shawnn@chromium.org>
There is only one set LED in reef, so with charger attached, LED behave as
charging LED; without charger, as power LED.
BUG=chrome-os-partner:55492
BRANCH=none
TEST=on reef proto, verified power led behavior is correct in s0/s3/g3
Change-Id: If6b83c46fc4b8b455531698177f559ca319d241a
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/366102
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
stm32f446 has two types of i2c blocks, the traditional
stm i2c, and "fast mode plus" i2c, which need different drivers.
This commit adds both, muxed in i2c-stm32f4, as the ec
codebase doesn't really support multiple types of the same interface.
BUG=chromium:608039
TEST=i2c works on all 4 channels
BRANCH=None
Change-Id: I6a9ac632f44142bd809ffee5782a192ae47af1f0
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368358
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BUG=chrome-os-partner:56247
BRANCH=None
TEST=Connect kevin to samus, run "pd 0 swap vconn", verify vconn state
shown by "pd 0 state" toggles. Also verify swaps instigated by samus
toggle vconn state on kevin.
Change-Id: Ieb8b7fe8b5e56a0d6fd29deba91efb2686c41ea4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371378
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
sweetberry is an stm32f446 based power monitoring
board, with 48 channels of INA current sense chips
BUG=chromium:608039
TEST=boots
BRANCH=none
Change-Id: If263bcee3a648ba3605f991999d481b7a0e2a1db
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370718
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
DIOM3 is no longer used. Remove it from gpio.inc
BUG=chrome-os-partner:55895,chrome-os-partner:55896
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I1f7aeab8135fa97aab04945b6a450e32903e2e84
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372405
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Previously this was only done when the board version is EVT or less
and when daughter card is inserted. However board version can not
be determined at this stage of power up since the function
board_get_version() relies on reading Board ID ADC and ADCs have not
yet been initialized.
This pull up can be removed in future board versions in which the
daughter card will always be in place and an internal pull-up will
no longer be needed.
BUG=chrome-os-partner:55488 chrome-os-partner:56039
BRANCH=none
TEST=verify board has no watchdog reset when daughter baord
is not connected. Also verify from EC log timestamps that
there is no delay of approximately 1 second between
"Inits done"and "KB init state"
Change-Id: I68eff923dd795b7b2f23f88028ee14d1e845b401
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/370958
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Turn off PP3300_A, PP5000_A, and PMIC when chipset_do_shutdown is called.
BUG=chromium:54962
TEST=Press power button for 9 seconds and confirm that PP3300_A, PP5000_A,
and PPVAR_VNN are at 0 volts. Also verify that system boots from G3 when
power button is pressed.
BRANCH=None
Change-Id: Ib8347873728e3940fd588599403c94d0f264f64c
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371340
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
There were a few things wrong with the way I2C pins were originally
set up:
- EC_I2C_SENSOR_SCL was moved from GPIOA0 to GPIO92.
- EC_I2C_GYRO_SCL/SDA and EC_I2C_POWER_SCL/SDA were swapped.
BUG=chrome-os-partner:53791
BRANCH=none
TEST=Motion sensors work now.
Change-Id: Id867c56b625da27e8ad82b503ae11173d7f855cc
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347754
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
This adds basic support for the stm32f446.
This consists of:
* New DMA model for stm32f4
* New clock domain support.
* MCO oscillator gpio export support.
* Flash support for irregular blocks.
BUG=chromium:608039
TEST=boots w/ correct clock, stm32f0 also boots.
BRANCH=None
Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363992
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
