scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-11 18:35:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

reef: Drive PMU_RSTBTN_N manually for proto boards

Browse Source 
Due to what appaers to be a leakage issue, this patch drives the
SYS_RST_ODL (aka PMU_RSTBTN_N) pin low for 1sec while the power
state transitions from S3 to S0.

This is a workaround for a proto board issue that prevents the SoC
from booting.

BUG=chrome-os-partner:53791
BRANCH=none
TEST=SoC boots with CL:347754 applied on proto and EVT boards

Change-Id: I88c3ccf18280acf5dfe3b99f99483dc4e4e27873
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372044
Reviewed-by: Martin Roth <martinroth@chromium.org>
This commit is contained in:
David Hendricks
2016-08-17 13:08:27 -07:00
committed by chrome-bot
parent 9342bb62d7
commit 68eb480a88
1 changed files with 16 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
board/reef/board.c
View File

@@ -560,6 +560,22 @@ static void board_chipset_startup(void)
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
#if IS_PROTO == 1
/*
* FIXME: This is a workaround for chrome-os-partner:53791. As per comment #53
* this issue should not occur on boards newer than proto.
*/
static void drive_sys_rst_odl_high(void)
{
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_HIGH);
CPRINTS("SYS_RST_ODL driven high");
msleep(1000);
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_ODR_HIGH);
CPRINTS("SYS_RST_ODL left floating (open-drain)");
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, drive_sys_rst_odl_high, HOOK_PRIO_DEFAULT);
#endif
/* Called on AP S3 -> S5 transition */
static void board_chipset_shutdown(void)
{