The ANX7447 has a sink/source control lines which can be connected to
a PPC. The NX20P3483 PPC requires this control to set it's sink/source
switch control. The ANX7447 contols these lines via the tcpci COMMAND
register. This CL adds new tcpm_set functions to set either SNK or SRC
control via the COMMAND register.
BUG=b:77583452
BRANCH=NONE
TEST=Tested on port 0 of Yorp with an external charger. Prior to this
CL the PPC would remain in standby state because both snk/src control
remained low. With these changes, verifed that snk_ctrl is driven high
and vbus_sink_enable() function no longer returns an error.
Change-Id: Icbea0d3edb63ad19f3d2c76636208497b6939a72
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/996239
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The new option allows to retrieve CCD information from the device. It
is reported similar to the way it is reported on the Cr50 console with
a few deviations:
- current capability setting is spelled out (instead of stating that
it is at default);
- default capability setting is reported only if it is different from
the current value.
- a bitmap of enabled capabilities is added in the end for ease of
verifying CCD state during factory process.
BRANCH=cr50, cr50-mp
BUG=b:72718383
TEST=ran the command on a Coral device:
$ gsctool -a -I
State: Locked
Password: None
Flags: 000000
Capabilities, current and default:
UartGscRxAPTx Y Always
UartGscTxAPRx Y Always
UartGscRxECTx Y Always
UartGscTxECRx - IfOpened
FlashAP - IfOpened
FlashEC - IfOpened
OverrideWP - IfOpened
RebootECAP - IfOpened
GscFullConsole - IfOpened
UnlockNoReboot Y Always
UnlockNoShortPP Y Always
OpenNoTPMWipe - IfOpened
OpenNoLongPP - IfOpened
BatteryBypassPP Y Always
UpdateNoTPMWipe Y Always
I2C - IfOpened
FlashRead Y Always
CCD caps bitmap: 0x16607
- then took the device through 'ccd open' sequence and tried again,
observed that all capabilities were set to 'Y' and caps bitmap was
set to 0x1ffff.
- then on the Cr50 console modified UnlockNoShortPP capability to be
set 'UnlessLocked', ran the command again, observed the default
value (Always) reported.
- locked the CCD on Cr50 console, ran the command one more time:
$ gsctool -a -I
State: Locked
Password: None
Flags: 000000
Capabilities, current and default:
UartGscRxAPTx Y Always
UartGscTxAPRx Y Always
UartGscRxECTx Y Always
UartGscTxECRx - IfOpened
FlashAP - IfOpened
FlashEC - IfOpened
OverrideWP - IfOpened
RebootECAP - IfOpened
GscFullConsole - IfOpened
UnlockNoReboot Y Always
UnlockNoShortPP - UnlessLocked (Always)
OpenNoTPMWipe - IfOpened
OpenNoLongPP - IfOpened
BatteryBypassPP Y Always
UpdateNoTPMWipe Y Always
I2C - IfOpened
FlashRead Y Always
CCD caps bitmap: 0x16207
Change-Id: I0fd5e6bd9402ae518e3f2a3ed82589f8696dfd44
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/999826
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It is important for the OS to be able to find out the state of CCD and
current capabilities settings of the device.
This patch defines a structure to use to report information about CCD
state from Cr50 to the host and adds a CCD vendor subcommand to allow
to retrieve the information from Cr50.
Some structure and variable definitions had to be moved into the .h
file to make it possible to share them between Cr50 and gsctool.
BRANCH=cr50, cr50-mp
BUG=b:72718383
TEST=with the following patch applied verified that CCD info is
properly reported. Also verified that other CCD subcommands still
work as advertised.
Change-Id: I4a783e6817ed364b9e64522ebbe968d4a657a84c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/999825
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Returns an error if the ODR set is less than 13Hz instead of silently
put the sensor in suspend mode.
BUG=b:77601149
BRANCH=None
TEST=Check with accelrate we get an error instead of
"Data rate for sensor 0: 0"
Change-Id: Iead740f4205bbce1cfbccf2407f2a3a0dcf0ddaf
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1000399
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Touch the watchdog during init to prevent it from firing
prematurely during HOOK_INIT processing before the tasks are
started and watchdog_reload() will be called with HOOK_TICK.
BUG=b:77336348
BRANCH=eve,poppy,fizz,reef,kevin
TEST=run stress test for several days:
while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done
Change-Id: I79e744a4678ab1808870d0e7647d2ce273ddeb8f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1001532
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With 3 binary strapping pins, we only have 7 available board ids:
000, 001, 010, 011, 100, 101, 110, 111.
Let's make the MSB of board id tristate. So we can have 4 more
board ids to use:
Z00, Z01, Z10, Z11.
BUG=b:77731277
BRANCH=poppy
TEST=build nautilus
Change-Id: I7aebb89437d2ccb9eea6c477155b25d964983232
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1000875
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
During watchdog initialization, the driver doesn't disable ITIM16
module which used for detecting watchdog timeout before updating
new preload value. Although the ITEN bit on reset is zero, it caused
preload value is not updated to module successfully since ITEN won't
be reset (ITIM16 is still enabled) in sysjump case.
Despite WDCNT will be reloaded by touching watchdog in HOOK_TICK
hook function later, it's better to disable any ITIM16 module before
updating ITCNT register.
BRANCH=none
BUG=b:77336821
TEST=No build errors for npcx5 series.
Change-Id: I19baa47bca347b9dca2fc1dcaacca81519facf21
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/999458
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The upcoming cr50-codesigner change will allow to use it for swapping
arbitrary blobs in the Cr50 image before signing.
Let's use this feature to replace test RMA public key with the prod
one.
BRANCH=cr50, cr50-mp
BUG=b:73296144
TEST=with the rest of the patches in place verified that invoking make
with CR50_SWAP_RMA_KEYS=1 causes swapping the RMA public key in
the generated image.
Change-Id: I4c9994c1a542f456b24d2066ecada9f92f1bfaf3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/996514
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Increase the size from 1024 to 4096 to reduce the likelihood of
overflows. To make space for the larger buffer, we reduce
CONFIG_ACCEL_FIFO to 512 entries (from 1024 entries: saves 4096
bytes of RAM).
grep shared_mem_buf build/lux/RW/ec.RW.smap
Before this patch:
200c74e0 D __shared_mem_buf
After this patch:
200c70e0 D __shared_mem_buf
(we saved 1024 bytes of RAM)
BRANCH=poppy
BUG=b:77159941
TEST=Flash lux, see that we do not lose EC logs in /var/log/cros_ec.log.
Change-Id: I320c370369364b280e59f490a86f057fbb502da3
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/983080
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since the last update of the 'fpcapture' debug console command, the
requested capture mode was ignored.
Fix the 2 identically-named variables stepping on each other
(dear compiler, why are you so distracted too ?)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:72360575
TEST=on ZerbleBarn, run 'fpcapture 0' and 'fpcapture 1'
Change-Id: I1fefd24b988f0db8bcbb90cc3370135d01cbddee
Reviewed-on: https://chromium-review.googlesource.com/999600
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
This is based on the initial code from Caveh here:
https://chromium-review.googlesource.com/959861
Most things are functional, with some workarounds for P0 boards.
The type-c hotplug is not working in this commit, the HPD will be
run from the tcpm in the next board build. For now we might be
able to get it working on P0 with some more tweaking..
The other known issue is that the battery takes ~2 seconds to
come back online after a cutoff (the auto-power-on timeout is
one second so the board will not power on like it should) and
sometimes the battery is not responding properly on i2c and it
requires an EC reset.
BUG=b:75070158
BRANCH=none
TEST=tested on P0 boards
Change-Id: I438cb93b78d6f501426842d6cbe3d6a994563358
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/982498
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
If we don't enable the SNK mode before leaving dead battery mode
(which does keep the inflow path open), then we will brown out
our only source of power.
BRANCH=none
BUG=b:77561535
TEST=yorp can boot into ec without battery
Change-Id: I095e3cb1ed466fd6497bbc9e7b6851fc92005c75
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/999024
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Swapping binary blobs in the image post compilation/linking is not
working quite as expected, because some of the const data values seem
to be inlined by the compiler, the values are not looked up at run
time.
This happens to the RMA public key ID field, which is just one byte in
size. Marking the field 'volatile' seems to be fixing the issue.
BRANCH=cr50, cr50-mp
BUG=b:73296144
TEST=with the rest of the patches applied public key substitution
between test and prod works as expected.
Change-Id: I12d5d1243e7988ab59bf3bba8cdfa46f27116bd2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/996513
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Source code for Cr50 codesigner has been added to the chroot and the
executable is installed as /usr/bin/cr50-codesigner when cros sdk is
created/updated.
Let's use the 'official' version instead of outdated local one.
BRANCH=cr50,cr50-mp
BUG=b:73296144
TEST=verified that properly signed Cr50 images can be built.
Change-Id: Ibc68340a26011c7d5ac028bbee73cd0f2c39c291
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/996512
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Port 0 uses the Anx7447. This CL updates the tcpc config to use the
Anx7447 driver instead of the Anx74xx driver.
BUG=b:74127309
BRANCH=NONE
TEST=make -j BOARD=yorp and verified that when connected external type
C charger to port 0 it reaches SNK_READY
Change-Id: I96967a1d272fcda079280ba6d2f0eb5ed8e3dd7f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982894
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Enable Gyro and collect data with FIFO.
BUG=b:73546254
BRANCH=master
TEST=Check gyro data is correct when enabled.
Run CTS test: cheets_CTS_N.7.1_r15.x86.CtsHardwareTestCases
Change-Id: I41321cfc8e7b4f8a006ee45c3a9d11305761315d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added FIFO support to Acc and Gyro with
watermark interrupt management.
Watermark is configurable setting macro
CONFIG_ACCEL_FIFO_THRES properly (board.h)
BUG=b:73546254
BRANCH=master
TEST=Pass CTS test cheets_CTS_N.7.1_r15.x86.CtsHardwareTestCases
on meowth.
TEST=Tested on discovery (target stmems) BOARD with LSM6DSM
connected to EC i2c master bus.
Using motion sense console commands is possible to:
- enable sensor (accelinit 0, accelinit 1 for acc and gyro)
- set ODR (accelrate 0 x, accelrate 1 y where x, y are mHz)
- show sensor data (accelinfo on <time> where time is in ms)
Using this procedure is possible to see Green Led of Discovery Board
Blinking each time an interrupt from FIFO arrives. To be sure to
generate interrupt is better to use high ODR and low time in accelinfo.
Change-Id: Icf95b0e889dc806206b8ca50e74636e6a2441a18
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/467326
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This patch allows chips which run code in RAM to erase or write
regions even if they're active.
BUG=b:77306460
BRANCH=none
TEST=flashrom -p ec -w /tmp/ec.bin on Fizz
Change-Id: Ib536b250dde78283513acb942507c67da0a6f622
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/997022
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The testlab will be running rma open on a bunch of devices. This change
adds a script for them to use.
The script handles things like finding the cr50 console and converting
the rma_auth output into a full challenge url. The user can click on the
url and generate the authcode. They can input the generated authcode
back into the script. The script will check 'ccd' output to make sure
rma open succeeds.
BUG=none
BRANCH=none
TEST=on a reef and bob running 3.4, run the entire cr50_rma_open
process. Verify RMA open succeeds
Change-Id: I2c9aef565351b65848f29083cd1e2c1f6e77e2a4
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/994417
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.
Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.
BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
handler), check that panicinfo contains a sensible PC in r5
after reset.
Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When flash_ec script is run from /usr/bin it could not find
the ec source directory to calculate the basebord. Handle flash_ec
running from /usr/bin by using the default chroot source layout to
find ec platform dir. If dir is not present, then skip baseboard
check
BRANCH=none
BUG=b:77128456
TEST=sudo emerge ec-devutils && flash_ec --board=yorp
Change-Id: Ib7766e5c7ca701f0a209c6e6e6c1a192284b9d0b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/992993
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds execution-in-ram, opposite of XIP: execution-in-place
(a.k.a. XIP) to the EC features. It can be currently implied by
CONFIG_EXTERNAL_STORAGE.
BUG=b:77306460
BRANCH=none
TEST=Verify ectool prints EXEC_IN_RAM on Fizz.
Change-Id: I4a7fb3b267864debe59fd211956371eceac57613
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995968
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch clarifies the logic which determines whether we perform EFS
or not and print different messages for each case.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I5588018a3594be2bcad84a2f74f805b76a195f85
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/996398
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Use RMA public key definition generated based on the binary blob
containing the key and key ID.
Key generation is controlled by the make file in common/, but actual
key blob comes from the board directory.
The structure holding the key and key ID is being modified to allow
initialization using a flat array.
No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and
CONFIG_RMA_AUTH_SERVER_KEY_ID.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST='make buildall' still succeeds.
test RMA server generated authentication codes are accepted when
unlocking RMA.
Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The semantics in the EC code base are that CONFIG_INTERNAL_STORAGE
implies eXecute-In-Place semantics (XIP). Add a comment to make that
abundantly clear.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80152eeb41dd35716f4c09ffd1753ae128aa7d2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Driver implements TCPC for ANX7447 chip. Enable Type C
port for USB and DP alt mode.
BUG=b:73793947
BRANCH=NONE
TEST=tested compiled binary for pdeval-stm32f072 board with this patch.
Power contract establishment, port role swap, DP alt mode works fine.
Change-Id: Ic11e499fc5fb4aba7732c75e4cb2fee54828c616
Reviewed-on: https://chromium-review.googlesource.com/956790
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
On yorp, the PS8751 TCPC resets its event mask when it goes into low
power mode which turns off the VBUS detection event mask. Since the
first interrupts after lower power mode should contain the vbus
changed interrupt we miss it.
We have tried many different permutations of resetting the event mask
on reset without achieving 100% detection success.
The PPC Vbus detection code calls out to the PPC over i2c every time
vbus level is checked; applying that strategy for TPCPs make the
detection much more robust.
BRANCH=none
BUG=b:77458917
TEST=yorp detect vbus on insertion every time with PS8751
Change-Id: I15b5f2ee016f68bac9e4bf4d5d89bbaef323f131
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/993394
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This patch brings in both prod and test RMA server public keys as two
binary files.
A bash script for converting binary blob into C definition is also
provided.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST=none yet
Change-Id: I2edd78164b8c912408ac7eda2e0a3a0262a8e81f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990782
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a specific option for it83xx chip and is used to
include EC2I module.
And we won't need it without LPC module enabled, so just
depend on CONFIG_LPC.
BUG=none
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/987674
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the wrong battery profile is loaded into max17055, we need
to be able to recover it after EC POR by reloading the correct profile.
BUG=b:77491650
BRANCH=scarlet
TEST=First, unplug/replug battery many times until I see
the battery profile loaded is wrong (1/20).
Second, make sure after a hard reset the correct battery profile
is loaded.
Change-Id: Iabb24fc75d31b9ce87bfb835e03549f4726903ed
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/991192
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
__builtin_ffs takes an int as argument, and, therefore, does not
find bits >= 32. Fix this up when CONFIG_HOST_EVENT64.
BUG=b:69329196
BRANCH=fizz,poppy
TEST=Patch coreboot to add bit 33 in SCI mask, add EC code to send
such events, EC does not watchdog anymore
Change-Id: If868095f19fe1940b4f5924cf669a719f9535991
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/989514
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We want to be able to replace RMA public key and its key ID in the elf
module before signing. Let's make sure they are packed together for
ease of find and replace operation.
BRANCH=cr50, cr50-mp
BUG=b:73296144
TEST=built an image, verified that RMA unlock still works.
Change-Id: I1a8e155391421f32b7422f11ab2a5f53d1ddd0ac
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990781
Reviewed-by: Randall Spangler <rspangler@chromium.org>
